PIC18F6520-I Datasheet, PDF (340/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-22: MASTER SSP I²C BUS DATA REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
102 TR
SDA and SCL
Rise Time
100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
—
20 + 0.1 CB
—
1000
300
300
ns CB is specified to be from
ns ^{10 to 400 pF}
ns
103 TF
SDA and SCL
Fall Time
100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
—
20 + 0.1 CB
—
300 ns CB is specified to be from
300 ns ^{10 to 400 pF}
100 ns
90
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) —
ms ^{Repeated Start condition}
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first
Hold Time
400 kHz mode 2(TOSC)(BRG + 1) —
ms ^{clock pulse is generated}
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
106 THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
0
0
TBD
— ns
0.9 ms
—
ns
107 TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
250
100
TBD
—
ns (Note 2)
—
ns
—
ns
92
TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
109 TAA
Output Valid
100 kHz mode
—
3500 ns
from Clock
400 kHz mode
—
1000 ns
1 MHz mode⁽¹⁾
—
—
ns
110 TBUF Bus Free Time 100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
4.7
1.3
TBD
— ms Time the bus must be free
—
ms ^{before a new transmission}
can start
— ms
D102 CB
Bus Capacitive Loading
—
400 pF
Note 1: Maximum pin capacitance = 10 pF for all I²C pins.
2: A fast mode I²C bus device can be used in a standard mode I²C bus system, but parameter #107 ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
DS39609B-page 338
 2004 Microchip Technology Inc.