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| PIC18F6520-I Datasheet, PDF (210/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D | |||
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PIC18F6520/8520/6620/8620/6720/8720
18.3 USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTAx<4>). In
addition, enable bit SPEN (RCSTAx<7>) is set in order
to configure the appropriate I/O pins to CK (clock) and
DT (data) lines, respectively. The Master mode indi-
cates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting bit
CSRC (TXSTAx<7>).
18.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available). Once the
TXREGx register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREGx is empty and
interrupt bit TXxIF (PIR1<4> for USART1, PIR3<4> for
USART2) is set. The interrupt can be enabled/disabled
by setting/clearing enable bit TXxIE (PIE1<4> for
USART1, PIE3<4> for USART2). Flag bit TXxIF will be
set, regardless of the state of enable bit TXxIE and can-
not be cleared in software. It will reset only when new
data is loaded into the TXREGx register. While flag bit
TXxIF indicates the status of the TXREGx register,
another bit TRMT (TXSTAx<1>) shows the status of the
TSR register. TRMT is a read-only bit, which is set
when the TSR is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory, so it is not available to the user.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 âUSART Baud Rate
Generator (BRG)â).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREGx register.
Note:
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE RBIE
GIEL
TMR0IF INT0IF
RBIF
0000 0000 0000 0000
PIR1
PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
PIR3
â
â
RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
â
â
RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
IPR3
RCSTAx(1)
â
SPEN
â
RC2IP
RX9 SREN
TXREGx(1) USART Transmit Register
TXSTAx(1) CSRC
TX9
TXEN
SPBRGx(1) Baud Rate Generator Register
TX2IP
CREN
SYNC
TMR4IP
ADDEN
â
CCP5IP
FERR
BRGH
CCP4IP
OERR
TRMT
CCP3IP
RX9D
TX9D
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
Legend:
Note 1:
x = unknown, â = unimplemented, read as â0â. Shaded cells are not used for synchronous master transmission.
Register names generically refer to both of the identically named registers for the two USART modules, where âxâ
indicates the particular module. Bit names and Reset values are identical between modules.
DS39609B-page 208
 2004 Microchip Technology Inc.
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