PIC18F6520-I Datasheet, PDF (104/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
9.6 INT0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered:
either rising, if the corresponding INTEDGx bit is set in
the INTCON2 register, or falling, if the INTEDGx bit is
clear. When a valid edge appears on the RBx/INTx pin,
the corresponding flag bit, INTxF, is set. This interrupt
can be disabled by clearing the corresponding enable
bit, INTxE. Flag bit, INTxF, must be cleared in software
in the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1, INT2 and
INT3) can wake-up the processor from Sleep if bit
INTxIE was set prior to going into Sleep. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
The interrupt priority for INT, INT2 and INT3 is deter-
mined by the value contained in the interrupt priority
bits: INT1IP (INTCON3<6>), INT2IP (INTCON3<7>)
and INT3IP (INTCON2<1>). There is no priority bit
associated with INT0; it is always a high priority
interrupt source.
9.7 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ters (FFFFh → 0000h) will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2<2>). See
Section 11.0 “Timer0 Module” for further details on
the Timer0 module.
9.8 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9 Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, Status and BSR registers
are saved on the fast return stack. If a fast return from
interrupt is not used (see Section 4.3 “Fast Register
Stack”), the user may need to save the WREG, Status
and BSR registers in software. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1 saves and restores the WREG, Status and
BSR registers during an Interrupt Service Routine.
EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP
MOVFF STATUS, STATUS_TEMP
MOVFF BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR
MOVF W_TEMP, W
MOVFF STATUS_TEMP, STATUS
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
DS39609B-page 102
 2004 Microchip Technology Inc.