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PIC18F6520-I Datasheet, PDF (255/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D
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PIC18F6520/8520/6620/8620/6720/8720
FIGURE 23-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
OSC1
CLKO(4)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST(2)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency(3)
GIEH bit
(INTCON<7>)
Processor in
Sleep
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Inst(PC) = Sleep
Instruction
Executed
Inst(PC - 1)
PC+2
Inst(PC + 2)
Sleep
PC+4
PC+4
Inst(PC + 4)
Inst(PC + 2)
PC + 4
Dummy Cycle
0008h
Inst(0008h)
Dummy Cycle
000Ah
Inst(000Ah)
Inst(0008h)
Note
1: XT, HS or LP Oscillator mode assumed.
2: GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
4: CLKO is not available in these oscillator modes, but shown here for timing reference.
23.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro® devices. The user program memory is
divided on binary boundaries into individual blocks,
each of which has three separate code protection bits
associated with it:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 23-3.
In the PIC18FXX20 family, the block size varies with
the size of the user program memory. For PIC18FX520
devices, program memory is divided into four blocks of
8 Kbytes each. The first block is further divided into a
boot block of 2 Kbytes and a second block (Block 0) of
6 Kbytes, for a total of five blocks. The organization of
the blocks and their associated code protection bits are
shown in Figure 23-3.
For PIC18FX620 and PIC18FX720 devices, program
memory is divided into blocks of 16 Kbytes. The first
block is further divided into a boot block of 512 bytes
and a second block (Block 0) of 15.5 Kbytes, for a total
of nine blocks. This produces five blocks for 64-Kbyte
devices and nine for 128-Kbyte devices. The organiza-
tion of the blocks and their associated code protection
bits are shown in Figure 23-4.
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
300008h CONFIG5L CP7(1) CP6(1) CP5(1) CP4(1)
300009h
30000Ah
CONFIG5H CPD
CPB
—
—
CONFIG6L WRT7(1) WRT6(1) WRT5(1) WRT4(1)
30000Bh
30000Ch
CONFIG6H WRTD WRTB WRTC
—
CONFIG7L EBTR7(1) EBTR6(1) EBTR5(1) EBTR4(1)
30000Dh CONFIG7H —
EBTRB
—
—
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices.
Bit 3
CP3
—
WRT3
—
EBTR3
—
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
 2004 Microchip Technology Inc.
DS39609B-page 253
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