46DR83200A Datasheet, PDF (9/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
Input DC logic level
Symbol Parameter
VIH(dc) dc input logic HIGH
VIL(dc) dc input logic LOW
Min.
VREF + 0.125
- 0.3
Max.
VDDQ + 0.3
VREF - 0.125
Units
V
V
Notes
Input AC logic level
Symbol Parameter
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Units Notes
Min.
Max.
Min.
Max
VIH (ac) ac input logic HIGH VREF + 0.250 VDDQ + Vpeak VREF + 0.200 VDDQ + Vpeak V 1
VIL (ac) ac input logic LOW VSSQ - Vpeak VREF - 0.250 VSSQ - Vpeak VREF - 0.200 V 1
Notes:
1. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.
AC Input Test Conditions
Symbol
Condition
Value
Units Notes
VREF
Input reference voltage
0.5 x VDDQ
V1
VSWING(MAX) Input signal maximum peak to peak swing
1.0
V1
SLEW
Input signal minimum slew rate
1.0
V/ns 2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to
VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the
negative transitions.
AC input test signal waveform
V_SWING(MAX)
Falling Slew =
DTF
V_REF - V_IL(ac) max
DTF
DTR
Rising Slew =
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
V_IH(ac) min - V_REF
DTR
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. D
08/16/2012