46DR83200A Datasheet, PDF (17/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
Timing Parameters by Speed Grade (DDR2-400 and DDR2-533)
(For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.)
Parameter
Clock cycle time, CL=x
CK HIGH pulse width
CK LOW pulse width
DQS latching rising transitions to associated clock
edges
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Symbol
tCK(avg)
tCH(avg)
tCL(avg)
tDQSS
tDSS
tDSH
DDR2-400
Min. Max.
5000
8000
0.48
0.52
0.48
0.52
- 0.25
0.25
0.2
–
0.2
–
DDR2-553
Min. Max
3750 8000
0.48
0.52
0.48
0.52
- 0.25 0.25
Units Notes
ps 35, 36
tCK(avg) ^{35, 36}
tCK(avg) ^{35, 36}
30
tCK(avg)
0.2
– tCK(avg) ³⁰
0.2
– tCK(avg) ³⁰
DQS input HIGH pulse width
tDQSH
0.35
–
0.35
– tCK(avg)
DQS input LOW pulse width
tDQSL
0.35
–
0.35
– tCK(avg)
Write preamble
tWPRE
0.35
–
0.35
– tCK(avg)
Write postamble
Address and control input setup time
Address and control input hold time
Control & Address input pulse width for each input
DQ and DM input setup time (differential strobe)
DQ and DM input hold time (differential strobe)
DQ and DM input setup time (single-ended strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input pulse width for each input
DQ output access time from CK/CK
DQS output access time from CK/ CK
Data-out high-impedance time from CK/ CK
DQS(DQS) low-impedance time from CK/ CK
DQ low-impedance time from CK/ CK
DQS-DQ skew for DQS and associated DQ signals
CK half pulse width
tWPST
0.4
0.6
0.4
tIS(base)
350
–
250
tIH(base)
475
–
375
tIPW
0.6
–
0.6
tDS(base)
150
–
100
tDH(base)
275
–
225
tDS1(base)
25
–
- 25
tDH1(base)
25
–
- 25
tDIPW
tAC
tDQSCK
tHZ
tLZ(DQS)
0.35
- 600
- 500
–
tAC min
–
+ 600
+ 500
tAC max
tAC max
0.35
- 500
- 450
–
tAC min
tLZ(DQ)
tDQSQ
tHP
2 x tAC
min
–
min (tCL,
tCH)
tAC max
350
–
2 x tAC
min
–
min (tCL,
tCH)
0.6
–
–
–
–
–
–
–
–
+ 500
+ 450
tAC
max
tAC
max
tAC
max
300
–
tCK(avg) 10
ps
5, 7, 9,
22, 29
ps
5, 7, 9,
23, 29
tCK(avg)
ps 6, 7, 8,
20, 28,
31
ps 6, 7, 8,
21, 28,
31
ps
6, 7, 8,
25
ps
6, 7, 8,
26
tCK(avg)
ps ⁴⁰
ps ⁴⁰
ps ^{18, 40}
18, 40
ps
18, 40
ps
ps 13
ps 11,12
DQ hold skew factor
DQ/DQS output hold time from DQS
Read preamble
tQHS
tQH
tRPRE
–
tHP -
tQHS
0.9
450
–
400
ps 12
– tHP - tQHS –
ps
1.1
0.9
1.1 tCK(avg) 19, 41
Read postamble
tRPST
0.4
0.6
0.4
0.6 tCK(avg) 19, 42
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. D
08/16/2012