46DR83200A Datasheet, PDF (29/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed
in the mode register set.
34. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800.
Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation.
Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Note that in DDR2-400 and DDR2-533, ‘tCK’ is used for both concepts.
ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2,
even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min.
35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock
jitter spec parameters'. The jitter specified is a random jitter meeting a Gaussian distribution.
Parameter
Symbol
Clock period jitter
tJIT(per)
Clock period jitter during DLL locking period
tJIT(per,lck)
Cycle to cycle clock period jitter
tJIT(cc
Cycle to cycle clock period jitter during DLL locking tJIT(cc,lck)
period
Cumulative error across 2 cycles
tERR(2per)
Cumulative error across 3 cycles
tERR(3per)
Cumulative error across 4 cycles
tERR(4per)
Cumulative error across 5 cycles
tERR(5per)
Cumulative error across n cycles, n = 6 ... 10,
inclusive
tERR(6-
10per)
Cumulative error across n cycles, n = 11 ... 50,
inclusive
tERR(11-
50per)
Duty cycle jitter
tJIT(duty)
DDR2-400
min max
-125 125
-100 100
-250 250
-200 200
-175 175
-225 225
-250 250
-250 250
-350 350
-450 450
-150 150
DDR2-533
min max
-125 125
-100 100
-250 250
-200 200
Units Notes
ps
35
ps
35
ps
35
ps
35
-175 175 ps
35
-225 225 ps
35
-250 250 ps
35
-250 250 ps
35
-350 350 ps
35
-450 450 ps
35
-125 125 ps
35
Parameter
Symbol
Clock period jitter
tJIT(per)
Clock period jitter during DLL locking period
tJIT(per,lck)
Cycle to cycle clock period jitter
tJIT(cc
Cycle to cycle clock period jitter during DLL locking tJIT(cc,lck)
period
Cumulative error across 2 cycles
tERR(2per)
Cumulative error across 3 cycles
tERR(3per)
Cumulative error across 4 cycles
tERR(4per)
Cumulative error across 5 cycles
tERR(5per)
Cumulative error across n cycles, n = 6 ... 10,
inclusive
tERR(6-
10per)
Cumulative error across n cycles, n = 11 ... 50,
inclusive
tERR(11-
50per)
Duty cycle jitter
tJIT(duty)
DDR2-667
min max
-125 125
-100 100
-250 250
-200 200
-175 175
-225 225
-250 250
-250 250
-350 350
-450 450
-125 125
DDR2-800
min max
-100 100
-80 80
-200 200
-160 160
Units Notes
ps
35
ps
35
ps
35
ps
35
-150 150 ps
35
-175 175 ps
35
-200 200 ps
35
-200 200 ps
35
-300 300 ps
35
-450 450 ps
35
-100 100 ps
35
Integrated Silicon Solution, Inc. — www.issi.com
29
Rev. D
08/16/2012