46DR83200A Datasheet, PDF (34/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
Mode Register (MR)
The mode register stores the data for controlling the various operating modes of the DDR2 SDRAM. It controls CAS
latency, burst length, burst sequence, test mode, DLL reset, and Write Recovery time (WR) to make DDR2 SDRAM
useful for various applications. The default value of the mode register is not defined, therefore the mode register must
be programmed during initialization for proper operation. The mode register is written by asserting LOW on CS, RAS,
CAS, WE, BA0 and BA1, while controlling the state of address pins A0 - A12. The DDR2 SDRAM should be in all
bank precharge state with CKE already HIGH prior to writing into the mode register. The mode register set command
cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as all banks are in
the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined
by A0 - A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst
address sequence type is defined by A3, CAS latency is defined by A4 - A6. The DDR2 does not support half clock
latency mode. A7 is a mode bit and must be set to LOW for normal MRS operation. A8 is used for DLL reset. Write
recovery time WR is defined by A9 - A11. Refer to the table for specific codes.
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/16/2012