46DR83200A Datasheet, PDF (22/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
DQS/
DQS
DQ
DM
DQS
t_DQSH
t_DQSL
DQS
t_WPRE
V_IH(ac)
D
V_IL(ac)
t_DS
DMin
D
V_IH(ac) ^tDS
DMin
V_IL(ac)
VIH(dc)
D
VIL(dc)
t_DH
DMin
Data Input (Write) Timing
t_CH
t_CL
CK
CK/CK
CK
t_WPST
D
t_DH
V_IH(dc)
DMin
V_IL(dc)
DQS
DQS/DQS
DQS
DQ
t_RPRE
t_DQSQmax
Q
t_QH
Data Output (Read) Timing
Q
Q
t_DQSQmax
t_RPST
Q
t_QH
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6. All voltages are referenced to VSS.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device They may be
guaranteed by device design or tester correlation.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
Specific Notes for Dedicated AC Parameters
1. User can choose which active power down exit timing to use via Mode Register Set [A12]. tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing.
2. AL = Additive Latency.
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and
tRAS(min) have been satisfied.
4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.
5. Timings are specified with command/address input slew rate of 1.0 V/ns. See Specific Notes on derating for other
slew rate values.
6. Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns. See
Specific Notes on derating for other slew rate values.
22
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/16/2012