46DR83200A Datasheet, PDF (26/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
4
3.5
3
2.5
2
1.5
1
Command/ _0.9
Address
0.8
Slew rate
0.7
(V/ns)
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
∆tIS and ∆tIH Derating Values for DDR2-667, DDR2-800
CK,CK Differential Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
∆tIS
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
150
94
180
124
210
154
143
89
173
119
203
149
133
83
163
113
193
143
120
75
150
105
180
135
100
45
130
75
160
105
67
21
97
51
127
81
0
0
30
30
60
60
-5
-14
25
16
55
46
-13
-31
17
-1
47
29
-22
-54
8
-24
38
6
-34
-83
-4
-53
26
-23
-60
-125
-30
-95
0
-65
-100
-188
-70
-158
-40
-128
-168
-292
-138
-262
-108
-232
-200
-375
-170
-345
-140
-315
-325
-500
-295
-470
-265
-440
-517
-708
-487
-678
-457
-648
-1000 -1125 -970 -1095 -940 -1065
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet
tIS(base) and tIH(base) value to the ∆tIS and ∆tIH derating value respectively. Example: tIS (total setup time) =
tIS(base) + ∆tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and
the first crossing of Vih(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal
slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is
later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line
to the actual signal from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and
the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal
slew rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to VREF(dc) level is used for derating value.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/
IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach
VIH/IL(ac).
For slew rates in between the values listed in the "Input Setup and Hold Time Derating" tables, the derating values
may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
26
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/16/2012