46DR83200A Datasheet, PDF (35/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
DDR2 SDRAM Mode Register Set (MRS)
Address
Field
BA1
BA0
Mode
Register
0
0
A12
PD
A11
A10
WR
A9
A12
Active power down exit time
0
Fast exit (use tXARD)
1
Slow exit(use tXARDS)
A11
A10
A9
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
WR(cycles)^*1
Reserved
2
3
4
5
6
Reserved
Reserved
A8
DLL
A7
TM
A8
DLL Reset
0
No
1
Yes
A6
A5
CAS
Latency
A4
A3
BT
A2
A1
Burst
Length
A0
A6
A5
A4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CAS Latency
Reserved
Reserved
Reserved
3²
4²
5²
6²
Reserved
A3
Burst Type
0
Sequential
1
Interleave
A7
Mode
0
Normal
1
Reserved
tCK (ns) for speed option²
-
-
-
-
-
-
-
-
-
-
-
-
5
5
5
5
5
3.75
3.75
3.75
5
3.75
3
3
5
3.75
3
2.5
-
-
-
-
A2
A1
A0
BL
0
1
0
4
0
1
1
8
Notes:
1. For DDR2-400/533, WR (write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock
cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = RU{ tWR[ns] / tCK[ns] }, where RU
stands for round up). For DDR2-667/800, WR min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR[cycles] =
RU{ tWR[ns] / tCK(avg)[ns] }, where RU stands for round up. The mode register must be programmed to this value. This is also used with tRP
to determine tDAL.
2. Speed bin determined. Refer to Key Timing Parameter table.
Integrated Silicon Solution, Inc. — www.issi.com
35
Rev. D
08/16/2012