46DR83200A Datasheet, PDF (37/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
Extended Mode Registers (EMR)
Extended Mode Register 1 (EMR1)
The EMR(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS
disable, OCD program, RDQS enable. The default value of the EMR(1) is not defined, therefore the extended mode
register must be programmed during initialization for proper operation. The EMR(1) is written by asserting LOW on
CS, RAS, CAS, WE, HIGH on BA0 and LOW on BA1, while controlling the states of address pins A0 - A12. The DDR2
SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register.
The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended
mode register. Mode register contents can be changed using the same command and clock cycle requirements during
normal operation as long as all banks are in the precharge state.
DLL enable/disable
The DLL must be enabled for normal operation. DLL enable is required during power-up and initialization, and upon
returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self
refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and
subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal
clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of
the tAC or tDQSCK parameters.
Integrated Silicon Solution, Inc. — www.issi.com
37
Rev. D
08/16/2012