46DR83200A Datasheet, PDF (14/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
IDD Specifications & Test Conditions (continued)
Symbol Conditions
-25E -3D -37C -5B Units
DDR2- DDR2- DDR2- DDR2-
800E 667D 533C 400B
IDD4R Operating burst read current; All banks open, Continuous burst reads,
IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
x8 345 300 240 190 mA
Address bus inputs are SWITCHING; Data pattern is same as IDD4W x16 310 275 240 190
IDD5B Burst refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval;
mA
CKE is HIGH, CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING;
x8 255 245 220 200
Data bus inputs are SWITCHING
x16 210 195 180 170
IDD6
Self refresh current;
CK and CK at 0 V; CKE ≤ 0.2 V;
Other control and address bus inputs are FLOATING;
x8 9
9
9
9 mA
Data bus inputs are FLOATING
x16 3
3
3
3
IDD7 Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL =
tRCD(IDD) - 1 x tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD),
tRCD = 1 x tCK(IDD);
CKE is HIGH, CS is HIGH between valid commands; Address bus
inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
mA
x8 290 280 270 265
x16 290 280 270 265
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of
EMR(1) bits 10 and 11.
5. For DDR2-667/800 testing, tCK in the Conditions should be interpreted as tCK(avg)
6. For A2 temperature grade with Ta > 85^oC, Idd2p and Idd3p (slow) are derated to 60% above the values shown, and Idd6 is derated to x2 above
the values shown.
7. Definitions for IDD
LOW = Vin ≤ VILAC(max)
HIGH = Vin ≥ VIHAC(min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at VREF = VDDQ/2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs
changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/16/2012