46DR83200A Datasheet, PDF (39/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
Extended Mode Register 2 (EMR2)
The Extended Mode Register 2 controls refresh related features. The default value of the EMR(2) is not defined,
therefore the mode register must be programmed during initialization for proper operation. The EMR(2) is written by
asserting LOW on CS, RAS, CAS, WE, HIGH on BA1 and LOW on BA0, while controlling the states of address pins
A0 - A12. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the
EMR(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the
EMR(2). Mode register contents can be changed using the same command and clock cycle requirements during
normal operation as long as all banks are in the precharge state.
Address
Field
BA1
BA0
A12^*1
Mode
Register
1
0
0
A11^*1
0
A10^*1
0
A9^*1
0
A8^*1
0
A7
SRF
A6^*1
0
A5
0
A4
0
A3
0
A2
A1
PASR^*3
A0
A7
High Temperature Self-Refresh Rate Enable
0
Disable
1
Enable^*2
A2
A1
A0
Partial Array Self Refresh for 4 Banks
BA[1:0]
0
0
0
Full Array
00, 01, 10, 11
0
0
1
1/2 Array
00, 01
0
1
0
1/4 Array
00
0
1
1
Not defined
–
1
0
0
3/4 array
01, 10, 11
1
0
1
1/2 array
10, 11
1
1
0
1/4 array
11
1
1
1
Not defined
–
EMR(2)
Notes:
1. A3-A6, A8-A12 are reserved for future use and must be set to 0 when programming the EMR(2).
2. Only Industrial and Automotive grade devices support the high temperature Self-Refresh Mode. The controller can set the EMR (2) [A7] bit to
enable this self-refresh rate if Tc > 85^oC while in self-refresh operation. Toper may not be violated.
3. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued.
Integrated Silicon Solution, Inc. — www.issi.com
39
Rev. D
08/16/2012