46DR83200A Datasheet, PDF (42/48 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 DDR2 DRAM

IS43/46DR83200A, IS43/46DR16160A
Clock Enable (CKE) Truth Table
Current
State²
CKE
Previous Cycle¹ Current Cycle¹
(N-1)
(N)
Power Down
L
L
L
H
Self Refresh
L
L
L
H
Bank(s)
H
L
Active
All Banks
H
L
Idle
H
L
H
H
Command (N)³
Action (N)³
RAS, CAS, WE,
CS
X
Maintain Power-Down
DESELECT or
NOP
Power Down Exit
X
Maintain Self Refresh
DESELECT or
NOP
Self Refresh Exit
DESELECT or
NOP
Active Power Down Entry
DESELECT or
NOP
Precharge Power Down
Entry
REFRESH
Self Refresh Entry
Refer to the Command Truth Table
Notes
11, 13, 15
4, 8, 11, 13
11, 15,16
4, 5, 9, 16
4, 8, 10, 11, 13
4, 8, 10, 11,13
6, 9, 11,13
7
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands
may be issued only after tXSRD (200 clocks) is satisfied.
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh cannot be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge
operations are in progress.
11. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the
time period of tIS + 2 x tCK + tIH.
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements
outlined in this datasheet.
14. CKE must be maintained HIGH while the DDRII SDRAM is in OCD calibration mode .
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMR(1) ).
16. VREF must be maintained during Self Refresh operation.
Data Mask Truth Table
Name (Functional)
Write enable
Write inhibit
DM DQs Note
L
Valid 1
H
X
1
Note:
1. Used to mask write data, provided coincident with the corresponding data
42
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/16/2012