BBT3821 Datasheet, PDF (8/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
FIGURE 2. DETAILED FUNCTIONAL BLOCK DIAGRAM (BIST OMITTED)
(See also Figure 4 & Figure 5 for MDIO and LASI blocks and Figure 6 for BIST operation)
XAUI
Equalizer
RXP0P/N Signal
Detect
RXP1P/N
Equalizer
Signal
Detect
Egress
RXP2P/N
Equalizer
Signal
Detect
RXP3P/N
Equalizer
Signal
Detect
PHY XS
(Serial)
Loopback
TXP0 P/N
TXP1 P/N
Ingress
TXP2 P/N
TXP3 P/N
20X or 10X
Clock
JTAG
MDIO Register, LASI & Common Logic
MDIO
Engine
I²C
BIST
LX4/CX4
CDR
10B/8B
Decoder
RX FIFO
Deskew
CDR
10B/8B
Decoder
RX FIFO
Deskew
CDR
10B/8B
Decoder
RX FIFO
Deskew
CDR
10B/8B
Decoder
RX FIFO
Deskew
PCS //
(PHY XS)
Loopback
8B/10B
Encoder,
AKR
Generator
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
Generator
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
Generator
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
Generator
TXFIFO &
Error and
Orderset
Detector
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
Generator
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
Generator
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
Generator
TXFIFO &
Error and
Orderset
Detector
8B/10B
Encoder,
AKR
Generator
PCS // Network
Loopback
RX FIFO
Deskew
10B/8B
Decoder
CDR
RX FIFO
Deskew
10B/8B
Decoder
CDR
RX FIFO
Deskew
10B/8B
Decoder
CDR
RX FIFO
Deskew
10B/8B
Decoder
CDR
TCX0 P/N
TCX1 P/N
Egress
TCX2 P/N
TCX3 P/N
PMA
Loop
back
Equalizer
Signal
Detect
RCX0 P/N
Equalizer,
Signal
Detect
RCX1 P/N
Ingress
Equalizer,
Signal RCX2 P/N
Detect
Equalizer,
Signal RCX3 P/N
Detect
Device Address 4 PHY XGXS
Device Address 3 PCS
Device Address 1 PMA/PMD
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