BBT3821 Datasheet, PDF (68/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

D.0.15
reset
T_RSTBIT
MDIO
engine
MDC
BBT3821
FIGURE 17. MDIO TIMING AFTER SOFT RESET (D.0.15)
Bit reset
(Internal States,
not observable)
T_MDRST
Engine reset, ignores
preamble
1^st preamble
bit
FIGURE 18. BEGINNING I²C NVR READ AT THE END OF RESET
condition RST wait train wait Read NVR
T_Update
T_Config
T_RESET
RSTN
T_TRAIN
Read DOM
SCL
(done)
SDA
Control Registers
T_WAIT
T_WAIT
Default Data
Auto-Config Data
FIGURE 19. I²C BUS INTERFACE PROTOCOL
SDA
MSB
SCL
S
or
Sr
1
2
START or
repeated START
condition
68
acknowledgement
signal from slave
acknowledgement
signal from receiver
byte complete,
interrupt within slave
clock line held low while
interrupts are served
7
8
9
ACK
Sr
1
2 3-8 9
or
ACK
P
STOP or
repeated START
condition