BBT3821 Datasheet, PDF (47/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
Table 78. IEEE 10GBASE-X PHY XGXS STATUS REGISTER
MDIO REGISTER ADDRESSES = 4.24 (4.0018’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
4.24.15:13
4.24.12
Reserved
PHY XS
Lane_Align
1 = 4 Lanes Aligned
0 = Lanes not aligned
1’b⁽¹⁾
RO
1 = Four 3G receive lanes (on egress path) are
aligned
4.24.11
Test_Pattern
Test Pattern Abilities
1’b
RO
1 = The device is able to generate test patterns for
10GBASE-X
4.24.10
PHYXSLpbk
Loopback Ability
1’b
RO
1 = Device is able to loopback
4.24.9:4
4.24.3
4.24.2
4.24.1
4.24.0
Reserved
Lane3 Sync
Lane2 Sync
Lane1 Sync
Lane0 Sync
1 = Lane is Synchronized
0 = Lane not Synchronized
1’b⁽¹⁾
1’b⁽¹⁾
1’b⁽¹⁾
1’b⁽¹⁾
RO
Reflects the PCS_SYNC byte alignment state
RO
machine condition; not valid if not enabled in
device (see Table 80)
RO
RO
Note (1): The status of these bits depends on the signal conditions. Default shown is for normal operation. The bits contribute to the RX Local Fault bit, see Table 77.
BIT
4.25.15:3
4.25.2
4.25.1:0
Table 79. IEEE 10GBASE-X PHY XGXS TEST CONTROL REGISTER
MDIO REGISTER ADDRESS = 4.25 (4.0019’h)
NAME
SETTING
DEFAULT R/W
DESCRIPTION
Reserved
PHY XS
TestPatEn
Receive Test Pattern 0’b
Enable
R/W 0 = Do not enable Receive test pattern
1 = Enable Receive test pattern
PHY XS TestPat
Type
Test pattern select (see 00’b
Table 72 for other test
patterns generated by
the BBT3821)
R/W 11 = Reserved
10 = Mixed frequency test pattern (Continuous /K/ = K28.5)
01 = Low frequency test pattern (repeat 0000011111 = K28.7)
00 = High frequency test pattern (repeat 0101010101 = D10.2)
VENDOR-SPECIFIC PHY XS REGISTERS (4.C000’H TO 4.C00B’H)
BIT
4.49152.15:14
4.49152.13:12
4.49152.11
4.49152.10
4.49152.9:8
4.49152.7
4.49152.6:5
Table 80. PHY XS CONTROL REGISTER 2
NAME
MDIO REGISTER ADDRESS = 4.49152 (4.C000’h)
SETTING DEFAULT⁽¹⁾ R/W
DESCRIPTION
Test Mode
00’b
00’b
R/W User should leave at 00’b
Reserved
PHY XS Clock
PSYNC
1’b
R/W 1 = Synchronize/align four lanes
0 = Do not synchronize/align four lanes
PHY XS CODECENA 0 = disable
1’b
1 = enable
R/W Internal 8B/10B Codec enable/disable
PHY XS CDET[1:0]
Comma Detect 11’b
Select.
PHY XS
DSKW_SM_EN
0 = disable⁽²⁾ 0’b
1 = enable
R/W These bits individually enable positive and negative disparity
“comma” detection.
11 = Enable both positive and negative comma detection
10 = Enable positive comma detection only
01 = Enable negative comma detection only
00 = Disable comma detection
R/W Enable De-skew state machine control ⁽³⁾ . Forced enabled
by PHY XS XAUI_EN. May not operate correctly unless the
PHY XS PCS_SYNC_EN bit is also set.
PHY XS RCLKMODE 11’b = Local
11’b
Reference
Clock⁽⁴⁾
R/W Other values should only be used if incoming data is
frequency-synchronous with the local reference clock⁽⁴⁾.
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