BBT3821 Datasheet, PDF (46/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
IEEE PHY XS REGISTERS (4.0 TO 4.25/4.0019’H)
Table 75. IEEE PHY XS CONTROL 1 REGISTER
MDIO REGISTER ADDRESS = 4.0 (4.0000’h)
BIT(S)
3.0.15
1.0.15
4.0.15
NAME
Reset
SETTING
1 = reset
0 = reset done, normal
operation
DEFAULT
0’b
R/W
DESCRIPTION
R/W SC Writing 1 to this bit will reset the whole chip,
including the MDIO registers.
4.0.14
PHY XS Loopback 1 = Enable loopback
0’b
R/W
Enable PHY XS loop back mode on all four lanes.
0 = Normal operation
3.0.13
4.0.13
Speed Select
1 = 10Gbps
1’b
RO
Operates at 10Gbps & above
4.0.12
4.0.11
Reserved
LOPOWER
0 = Normal Power
00’h
0’b
R/W
No Low Power Mode, writes ignored
4.0.10:7
3.0.6
4.0.6
Reserved
Speed Select
1 = 10Gbps
1’b
RO
Operates at 10Gbps & above
3.0.5:2
4.0.5:2
4.0.1:0
Speed Select
Reserved
0000 = 10Gbps
0’h
RO
Operates at 10Gbps
0’b
Table 76. IEEE PHY XS STATUS 1 REGISTER
MDIO REGISTER ADDRESS = 4.1 (4.0001’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.1.15:8 Reserved
00’h
4.1.7
Local Fault
1 = PHY XS Local Fault
0
RO
Derived from Register 4.0008’h
4.1.6:3
4.1.2
Reserved
Tx Link Up
1 = XGXS Tx Link Up
0 = XGXS Tx Link Down
0’h
1 ⁽¹⁾
RO LL⁽¹⁾
‘Up’ means XAUI-side signal level is OK, Byte
Synch and Lane-Lane Alignment have all
occurred
4.1.1
LoPwrAble
Low Power Ability
0
RO
Device does not support a low power mode
4.1.0
Reserved
0
Note (1): This bit is latched low on a detected Fault condition. It is set high on being read.
Table 77. IEEE PHY XS STATUS 2 DEVICE PRESENT & FAULT SUMMARY REGISTER
MDIO REGISTER ADDRESSES = 4.8 (4.0008’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
4.8.15:14
Device present 10 = Device present
10’b
RO When read as “10”, it indicates that a device is present at
this device address
4.8.13:12
Reserved
4.8.11
TX LocalFlt
1 = TX Local Fault; on Egress 0’b
channel
RO/ Lane Alignment or Byte Alignment not done, or Loss of
LH⁽¹⁾ Signal. From Reg. 4.24
4.8.10
RX LocalFlt
1 = RX Local Fault; on Ingress 0’b
channel
RO/ PLL lock failure (lack of RFCP/N signal)
LH⁽¹⁾
4.8.9:0
Reserved
Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI
registers 1.9003’h (bit 10, see Table 27) or 1.9004’h (bit 11, see Table 28)
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