BBT3821 Datasheet, PDF (63/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
AC and Timing Characteristics
All specifications assume T_C = 0°C to +85°C, and V_DDAC = V_DDAV = V_DD = V_DDA = 1.5V ± 5% (for the Standard Device) or V_DDAC = V_DDAV = V_DD
= V_DDA = 1.35V ± 4%(for the Low Power Device), V_DDPR between V_DD and 2.5V, unless otherwise specified.
Table 112. REFERENCE CLOCK REQUIREMENTS
SYMBOL
F_REF
∆F_REF
T_REFRF
DTC_REF
∆V_REF
V_CM
PARAMETER
Ref clock frequency range⁽¹⁾
Ref clock frequency offset
Ref clock Rise and Fall Time
Ref clock duty cycle
Ref Clock Voltage Swing⁽²⁾
Internal Common Mode Voltage
MIN
124.4
-100
45
300
TYP
50
V_DD/2
MAX
159.375
+100
1.5
55
1000
UNITS
MHz
ppm
ns
%
mV
V
Note (1): System requirements are normally much more restrictive, typically ± 100 ppm. This specification refers to the full reference clock frequency range over which
the BBT3821 will operate.
Note (2): Single-ended peak-to-peak swing.
Table 113. TRANSMIT SERIAL DIFFERENTIAL OUTPUTS (SEE Figure 9, Figure 10 AND Figure 11)
SYMBOL
PARAMETER
MIN
TYP
MAX
TCXnP/N and TXPxP/N output data rate
2.448
3.1875
T_DR
T_DF
T_DTOL
T_ODS
Differential Rise time (20%-80%)
Differential Fall time (20%-80%)
Differential Skew Tolerance
Lane to Lane Differential Skew ⁽²⁾
Differential Output Impedance
60
110
130
60
110
130
TBD
15
100
TX_RJ
Differential Return Loss (to 2.5GHz)
Random Jitter (RMS, 1100 pattern)⁽¹⁾
2.488Gbps
3.125Gbps
10
2
4.5
2.5
4.5
Total Jitter (RMS, PRBS⁷ pattern)
3.1875
2.488Gbps
TBD
TBD
8
3.125Gbps
6
8
3.1875
8
Note (1): Strictly the 1100 pattern causes a small additional non-random jitter, so that the true random jitter is slightly less than that shown.
Note (2): Parameter is guaranteed by design
UNIT
Gbps
ps
ps
ps
ps
Ω
dB
ps
ps
ps
ps
ps
ps
Table 114. RECEIVE SERIAL DIFFERENTIAL INPUT TIMING REQUIREMENTS (SEE Figure 11)
SYMBOL
PARAMETER
MIN
TYP
MAX
RCXnP/N & RXPnP/N Input Data Rate
2.448
3.1875
Input Rate deviation from Reference Clock
-200
+200
Bit Synchronization Time
2500
Frequency Lock after Power-up
2
T_DTOL
Input Differential Skew
75
T_DJ
Deterministic Jitter^(1,2)
2.488Gbps
TBD
3.125Gbps
0.7
3.1875
TBD
T_JI
Total jitter tolerance
2.488Gbps
3.125Gbps
TBD
0.88
3.1875
TBD
Note (1): Jitter specifications include all but 10^-12 of the jitter population.
Note (2): Near end driven by BBT3821 Tx without pre-emphasis.
UNITS
Gbps
ppm
bits
µs
ps
UI
UI
UI
UI
UI
UI
63