BBT3821 Datasheet, PDF (49/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
Table 81. PHY XS CONTROL REGISTER 3 (Continued)
MDIO REGISTER ADDRESS = 4.49153 (4.C001’h)
BIT
NAME
SETTING
DEFAULT⁽¹⁾ R/W
DESCRIPTION
4.49153.2:0
MF_CTRL
0 = BIST_ERR
1 = LOS
2,3 = Reserved
4 = TXFIFO_ERR
5 = AFIFO_ERR
6 = EFIFO_ERR
000’b
R/W
Control the meaning of Multi-function pins MF[3:0] of
the 4 lanes in the device selected by MF_SEL above
(bit 12)
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden by PHY XS XAUI_EN, see also Table 65.
Note (3): This state machine is implemented according toIEEE 802.3ae-2002 clause 48.
Table 82. PHY XS INTERNAL ERROR CODE REGISTER
MDIO REGISTER, ADDRESS = 4.49154 (4.C002’h)
BIT
NAME
SETTING
DEFAULT⁽¹⁾ R/W
DESCRIPTION
4.49154.15:8
4.49154.7:0
Reserved
PHY XS
ERROR
Desired Value⁽²⁾
FE’h
R/W
Error Code. These bits allow the internal FIFO
ERROR control character to be programmed.
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden to FE’h by PHY XS XAUI_EN, see Table 65 and Table 81.
Table 83. PHY XS INTERNAL IDLE CODE REGISTER
MDIO REGISTER ADDRESS = 4.49155 (4.C003’h)
BIT
NAME
SETTING
DEFAULT⁽¹⁾ R/W
DESCRIPTION
4.49155.15:8
Reserved
4.49155.7:0
PHY XS
Desired Value
07’h
XG_IDLE
R/W
IDLE pattern in internal FIFOs for translation
to/from XAUI IDLEs
Note (1): The default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
BIT
4.49156.15:13
4.49156.12
4.49156.11
4.49156.10
4.49156.9
4.49156.8
4.49156.7:4
4.49156.3
4.49156.2
4.49156.1
4.49156.0
Table 84. PHY XS MISCELLANEOUS LOOP BACK CONTROL REGISTER
MDIO REGISTER ADDRESS = 4.49156 (4.C004’h)
NAME
SETTING
DEFAULT R/W
DESCRIPTION
Reserved
Test LP
SLP_3
SLP_2
SLP_1
SLP_0
1 = enable
1 = enable PHY XS
Network Loopback
0 = disable
0’b⁽¹⁾
0’b⁽²⁾
0’b⁽²⁾
0’b⁽²⁾
0’b⁽²⁾
R/W
Serial Host Test Loopback
R/W
Internal PHY XS Serial Loop Back Enable for each
individual lane. When high, it routes the internal
XAUI Serial output to the Serial input.
Reserved
PLP_3
PLP_2
PLP_1
PLP_0
1 = enable System (“PCS”)
Parallel Loopback
0 = disable
0’b⁽²⁾
0’b⁽²⁾
0’b⁽²⁾
0’b⁽²⁾
R/W
PCS Parallel Loop Back Enable for each individual
lane. When high, it routes the XAUI Serial input to
the Serial output via the full PHY XS.
Note (1): Loopback is from XAUI Serial I/P to Serial O/P. Recommended use for test purposes only; no retiming or pre-emphasis is performed
Note (2): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
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