BBT3821 Datasheet, PDF (29/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
Table 29. XENPAK LASI STATUS REGISTER
MDIO REGISTER, ADDRESS = 1.36869 (1.9005’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
1.36869.15:4
Reserved
000’h
1.36869.3
1.36869.2
GPIO Alarm
RX_ALARM
1 = Alarm Condition is 0’b
Detected
0 = No Alarm Condition is
Detected
0’b
RO
Logic OR of signals in register
1.49169.[15:8] (1.C011h), which come
from GPIO pins.
RO
Logic OR of signals in register
1.36867 RX_ALARM Status register
1.36869.1
TX_ALARM
0’b
RO
Logic OR of signals in register
1.36868 TX_ALARM Status register
1.36869.0
LS_ALARM
0’b
RO
Link Status Logic change in AND of “PMD Signal
LH⁽¹⁾ OK” (1.10.0), “PCS Lane
Alignment” (3.24.12), and “PHY XS
Lane Alignment” (4.24.12)
Note (1): This bit is latched high on any change in the condition detected. It is reset low (cleared) on being read.
Table 30. XENPAK DOM TX_FLAG CONTROL REGISTER
BIT⁽¹⁾
NAME
MDIO REGISTER, ADDRESS = 1.36870 (1.9006’h)
SETTING
DEFAULT⁽²⁾ R/W
DESCRIPTION
1.36870.15:8
Reserved
000’h
1.36870.7
1.36870.6
TTmp_Hi
1 = Enable Alarm
0’b
0 = Disable Alarm
TTmp_Lo
0’b
R/W
Transceiver Temp High Alarm Enable
R/W
Transceiver Temp Low Alarm Enable
1.36870.5:4
Reserved
0’h
R/W
1.36870.3
1.36870.2
LBC_Hi
1 = Enable Alarm
0’b
0 = Disable Alarm
LBC_Lo
0’b
R/W
Laser Bias Current High AlarmEnable
R/W
Laser Bias Current Low Alarm Enable
1.36870.1
LOP_Hi
0’b
R/W
Laser Output Power High Alarm Enable
1.36870.0
LOP_Lo
0’b
R/W
Laser Output Power Low Alarm Enable
Note (1): These bits control (select) alarm signals (bits) in register 1.41072 (1.A070’h) to generate the TX_Flag bit of register 1.36868 (1.9004’h) to trigger TX_ALARM
and hence LASI.
Note (2): The default values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Table 31. XENPAK DOM RX_FLAG CONTROL REGISTER
BIT⁽¹⁾
NAME
MDIO REGISTER, ADDRESS = 1.36871 (1.9007’h)
SETTING
DEFAULT⁽²⁾ R/W
DESCRIPTION
1.36871.15:8
Reserved
000’h
1.36871.7
ROP_Hi
1 = Enable Alarm
0’b
0 = Disable Alarm
R/W
Receive Optical Power High Alarm
Enable
1.36871.6
ROP_Lo
0’b
R/W
Receive Optical Power Low Alarm
Enable
1.36871.5:0
Reserved
00’h
Note (1): These bits control (select) alarm signals (bits) in register 1.41073 (1.A071’h) to generate the RX_Flag bit of register 1.36867 (1.9003’h) to trigger RX_ALARM
and hence LASI.
Note (2): The default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
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