BBT3821 Datasheet, PDF (55/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

Pin Specifications
PIN#
T9/T8
NAME
RFCP/RFCN
C10
TXCLK20
BBT3821
TYPE
Input
LVPECL
Output
1.5V CMOS
Table 94. CLOCK PINS
DESCRIPTION
Differential Reference Input Clock. The reference input clock frequency is line rate
clock frequency divided by 20 (full rate mode) or 10 (half rate mode). The pins are
internally biased at VDDA/2, and should be AC coupled.
Transmit Clock Output. Divided-by-20 transmit clock output.
PIN#
T14/T15
P14/P15
M14/M15
K14/K15
H14/H15
F14/F15
D14/D15
B14/B15
NAME
TXP0P/TXP0N
TXP1P/TXP1N
TXP2P/TXP2N
TXP3P/TXP3N
RXP0P/RXP0N
RXP1P/RXP1N
RXP2P/RXP2N
RXP3P/RXP3N
Table 95. XAUI (XENPAK/XPAK/X2) SIDE SERIAL DATA PINS
TYPE
DESCRIPTION
Output CML Transmit Differential Pairs, Lane 0 to 3. CML High speed serial outputs.
Input CML
Receive Differential Pairs, Lane 0 to 3. CML High speed serial inputs. Differentially
terminated at 100Ω
PIN#
A2/A3
C2/C3
E2/E3
G2/G3
R2/R3
N2/N3
L2/L3
J2/J3
NAME
TCX0P/TCX0N
TCX1P/TCX1N
TCX2P/TCX2N
TCX3P/TCX3N
RCX0P/RCX0N
RCX1P/RCX1N
RCX2P/RCX2N
RCX3P/RCX3N
Table 96. PMA/PMD (CX4/LX4) SIDE SERIAL DATA PINS
TYPE
DESCRIPTION
Output CML Transmit Differential Pairs, Lane 0 to 3. CML High speed serial outputs.
Input CML
Receive Differential Pairs, Lane 0 to 3. CML High speed serial inputs. Differentially
terminated at 100Ω
PIN#
D12
B12
D8
C12
C8
NAME
TDI
TDO
TMS
TCLK
TRSTN
Table 97. JTAG INTERFACE PINS
TYPE
DESCRIPTION
Input (with pullup)
JTAG Input Data. 1.5V CMOS
Output (open drain)
JTAG Output Data. 1.5V CMOS, 2.5V Tolerant
Input (with pullup)
JTAG Mode Select. 1.5V CMOS
Input (with pulldown)
JTAG Clock. 1.2V CMOS, 2.5V Tolerant, with Schmitt trigger
Input (with pullup)
JTAG Reset. 1.5V CMOS
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