BBT3821 Datasheet, PDF (32/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
Table 35. XENPAK DOM EXTENDED CAPABILITY REGISTER
BIT
1.41071.15:8
NAME
Reserved
MDIO REGISTER, ADDRESS = 1.41071 (1.A06F’h)
SETTING
DEFAULT
00’h⁽¹⁾
R/W
DESCRIPTION⁽¹⁾
1.41071.7
1.41071.6
1.41071.5
1.41071.4
TT_Able
LBC_Able
LOP_Able
ROP_Able
1 = Indicates
Capability
Implemented
0 = Not
Implemented
RO
Transceiver Temp Monitoring Capable
RO
Laser Bias Current Monitoring Capable
RO
Laser Output Power Monitoring Capable
RO
Receive Optical Power Monitoring Capable
1.41071.3
AL_Able
RO
Alarm Flags for Monitored Quantities
1.41071.2
WN_Able
RO
Warning Flags for Monitored Quantities
1.41071.1
MON_LASI
RO
Monitoring Quantities Input to LASI
1.41071.0
Reserved
RO
Monitoring Capable
Note (1): These 1-byte register values are merely copied by the BBT3821 from the I²C address space on Power-up or RESET, or on a periodic or on-demand direct
DOM update operation (i.e. with Register bit 1.C018’h.2 Table 51 not set) under the control of Register 1.A100’h (Table 38). The BBT3821 takes no action as
a result of the values copied.
Table 36. XENPAK DOM ALARM FLAGS REGISTER
BIT
1.41072.15:8
NAME
Reserved
MDIO REGISTER, ADDRESS = 1.41072:3 (1.A070:1’h)
SETTING
DEFAULT R/W
00’h⁽¹⁾
RO
DESCRIPTION⁽¹⁾
1.41072.7
1.41072.6
TT_High
1 = Alarm Set
0’b
TT_Low
0 = Alarm Not Set
0’b
RO
Transceiver Temp High Alarm
RO
Transceiver Temp Low Alarm
1.41072.5:4
Reserved
00’b
1.41072.3
1.41072.2
LBC_High
1 = Alarm Set
0’b
LBC_Low
0 = Alarm Not Set
0’b
RO
Laser Bias Current High Alarm
RO
Laser Bias Current Low Alarm
1.41072.1
LOP_High
0’b
RO
Laser Output Power High Alarm
1.41072.0
LOP_Low
0’b
RO
Laser Output Power Low Alarm
1.41073.15:8
Reserved
00’h
1.41073.7
1.41073.6
ROP_High 1 = Alarm Set
0’b
ROP_Low
0 = Alarm Not Set
0’b
RO
Receive Optical Power High Alarm
RO
Receive Optical Power Low Alarm
1.41073.5:0
Reserved
00’h
Note (1): These 1-byte register values are copied by the BBT3821 from the I²C address space on Power-up or RESET, or on any DOM read operation. If the ‘Indirect
DOM Enable’ bit (Register bit 1.C018’h.2 Table 51) is not set, a four-lane external DOM device is expected to determine the values for these registers,
according to Section 11.3 in the XENPAK MSA Rev 3.0 specification. A single one-lane DOM device system will provide the values from the single DOM
device here. If the ‘Indirect DOM Enable’ bit is set, the values from the “Representative” (as set by Register bits 1.C018’h.1:0 in Table 51) lane DOM are
entered here. See “DOM Registers” on page 16. These bits are gated with the enable bits in 1.9006:7 (Table 30 & Table 31) and the LX4/CX4 select
LX4_MODE pin to drive bits 1.9004.1 & 1.9003.1 (Table 28 & Table 27), and if enabled via 1.9002 & 1.9001 (Table 25 & Table 24) to drive the LASI pin.
BIT
1.41076.15:8
1.41076.7
1.41076.6
1.41076.5:4
NAME
Reserved
TT_High
TT_Low
Reserved
Table 37. XENPAK DOM WARNING FLAGS REGISTER
MDIO REGISTER, ADDRESS = 1.41076:7 (1.A074:5’h)
SETTING
DEFAULT R/W
00’h⁽¹⁾
DESCRIPTION⁽¹⁾
1 = Warning Set
0’b
0 = Warn. Not Set
0’b
RO
Transceiver Temp High Warning
RO
Transceiver Temp Low Warning
00’b
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