BBT3821 Datasheet, PDF(36/75 Page) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

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BBT3821 Datasheet, PDF (36/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

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BBT3821

Table 47. GPIO PIN DIRECTION CONFIGURE REGISTER

MDIO REGISTER ADDRESS = 1.49168 (1.C010âh)

BIT

NAME

SETTING

DEFAULT

R/W

DESCRIPTION

1.49168.15:5

1.49168.4:0

Reserved

GPIO pins

configuration

1 = output

0 = input

00âh(1)

R/W

Controls whether GPIO pin is used as input or

output

Note (1): The value may be overwritten by the Auto-Configure operation (See âAuto-Configuring Control Registersâ on page 16 and Table 92 for details).

Table 48. GPIO PIN INPUT STATUS REGISTER

MDIO REGISTER ADDRESS = 1.49169 (1.C011âh)

BIT

NAME

SETTING

R/W

DESCRIPTION

1.49169.15:13

1.49169.12:8

Reserved

LASI I/P

value

1 = can trigger LASI (1)

0 = cannot trigger LASI

RO/LH XOR of GPIO Pin I/P and Invert register

1.49170.13:8.

1.49169.7:5

Reserved

1.49169.4:0

GPIO Pin I/P

Value

1 = Pin Hi

0 = Pin Lo

Original values from GPIO pins directly.

Note (1): If any of these bits is set to â1â, it triggers LASI if the corresponding bit in 1.49170.5:0 and the GPIO enable bit 1.36866.3 are set high.

Table 49. TX_FAULT & GPIO PIN TO LASI CONFIGURE REGISTER

MDIO REGISTER ADDRESS = 1.49170 (1.C012âh)

BIT

NAME

SETTING

DEFAULT R/W

DESCRIPTION

1.49170.15:14

1.49170.13

1.49170.12:8

Reserved

Invert TX_FAULT 1 = Pin Low,

0 = Pin High to trigger LASI

Invert LASI I/P

1 = Invert to LASI

0 = Straight to LASI

0âb(2)

00âh(2)

R/W

Control Polarity of TX_FAULT pin which will

trigger LASI (if enabled)

R/W

Control XOR of GPIO Pin I/P to LASI I/P

1.49170.7:5

1.49170.4:0

Reserved

Enable LASI I/P

1 = Enable (1)

0 = Do not Enable

00âh(2)

R/W

Enable the GPIO pin value to trigger

GPIO_ALARM to LASI

Note (1): If any of these bits is set to â1â, it triggers LASI if the corresponding bit in 1.49169.12:8 and the GPIO enable bit 1.36866.3 are set high. The polarity that will

trigger LASI is set by bits 1.49170.12:8 above.

Note (2): These values may be overwritten by the Auto-Configure operation (See âAuto-Configuring Control Registersâ on page 16 and Table 92 for details).

Table 50. GPIO PIN OUTPUT REGISTER

MDIO REGISTER ADDRESS = 1.49171 (1.C013âh)

BIT

NAME

SETTING

DEFAULT

R/W

DESCRIPTION

1.49171.15:5

1.49171.4:0

Reserved

GPIO Pin

Output

0 = Low

1 = High

00âh(1)

R/W

Controls GPIO pin level if set as output

Note (1): The value may be overwritten by the Auto-Configure operation (See âAuto-Configuring Control Registersâ on page 16 and Table 92 for details).

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