BBT3821 Datasheet, PDF (41/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
VENDOR-SPECIFIC PCS REGISTERS (3.C000’H TO 3.C00E’H)
Table 63. PCS CONTROL REGISTER 2
MDIO REGISTER ADDRESS = 3.49152 (3.C000’h)
BIT
NAME
SETTING
DEFAULT⁽¹⁾ R/W
DESCRIPTION
3.49152.15:14
Test Mode
00’b
00’b
R/W User should leave at 00’b
3.49152.13:12
Reserved
3.49152.11
PCS Clock PSYNC
1’b
R/W 1 = Synchronize/align four lanes
0 = Do not synchronize/align four lanes
3.49152.10
PCS CODECENA 0 = disable
1’b
1 = enable
R/W Internal 8B/10B PCS Codec enable/disable
3.49152.9:8
PCS CDET[1:0]
Comma Detect 11’b
Select
3.49152.7
3.49152.6:5
3.49152.4
PCS
DSKW_SM_EN
0 = disable⁽²⁾
0’b
1 = enable
PCS RCLKMODE⁽⁴⁾ 11’b = Local
11’b
Reference Clock
PCS_SYNC_EN
0 = disable⁽²⁾
0’b
1 = enable
R/W These bits individually enable positive and negative
disparity “comma” detection.
11 = Enable both positive and negative comma detection
10 = Enable positive comma detection only
01 = Enable negative comma detection only
00 = Disable comma detection
R/W Enable De-skew state machine control ⁽³⁾ . Forced enabled
by XAUI_EN. May not operate correctly unless the
PCS_SYNC_EN bit is also set.
R/W Other values should only be used if incoming data is
frequency-synchronous with the local reference clock⁽⁴⁾
R/W Enable 8b/10b PCS coding synchronized state machine⁽³⁾
to control the byte alignment (IEEE ‘code-group alignment’)
of the high speed de-serializer
3.49152.3
PCS IDLE_D_EN 1 = enabled
1’b
0 = disabled
R/W Enables IDLE vs. NON-IDLE detection for lane-lane
alignment. Overridden by XAUI_EN, see Table 64
3.49152.2
3.49152.1
PCS ELST_EN
PCS
A_ALIGN_DIS
1 = enabled
1’b
0 = disabled
1 = disabled⁽¹⁾ 1’b
0 = enabled
R/W Enable the elastic function of the receiver buffer
R/W Receiver aligns data on incoming “/A/” characters (K28.3).
If disabled (default), receiver aligns data on IDLE to non-
IDLE transitions (if bit 3 set). Overridden by XAUI_EN, see
Table 64
3.49152.0
PCS
CAL_EN
1 = enabled
1’b
0 = disabled
R/W Enable de-skew calculator of receiver Align FIFO
Note (1): The default values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden by PCS XAUI_EN, see Table 64 and Table 65.
Note (3): These state machines are implemented according to 802.3ae-2002 clause 48.6.2.
Note (4): If the RCLKMODE bits are set to 10’b, the internal XGMII clock from the PCS to the PHY XS is set to the recovered clock. If the PCS Clock PSYNC bit is set
(the default), the recovered clock from Lane 0 is used for all four lanes, if cleared, or if the RCLKMODE bits are set to 01’b or 00’b, each lane uses its own
recovered clock. If the incoming data is NOT frequency-synchronous with the local reference clock, data will be corrupted (occasional characters will be lost,
or repeated).
BIT
3.49153.15:12
3.49153.11
NAME
Reserved
PCS XAUI_EN
3.49153.10:8
3.49153.7
Reserved
EN_PCSLB_EN
Table 64. PCS CONTROL REGISTER 3
MDIO REGISTER ADDRESS = 3.49153 (3.C001’h)
SETTING
DEFAULT R/W
DESCRIPTION
1 = enable
0 = disable
1’b⁽¹⁾
R/W Enables all XAUI features per 802.3ae-2002. It is
equivalent to setting the configuration bits listed in
Table 65 (but does not change the actual value of the
corresponding MDIO registers’ bits).
0’b⁽¹⁾
Enable 3.0.14 Loopback Control ⁽²⁾
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