|
BBT3821 Datasheet, PDF (27/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer | |||
|
◁ |
BBT3821
XENPAK LASI AND DOM REGISTERS (1.9000âH TO 1.9007âH & 1.A000âH TO 1.A100âH)
Table 24. XENPAK LASI RX_ALARM CONTROL REGISTER
MDIO REGISTER, ADDRESS = 1.36864 (1.9000âh)
BIT
NAME
SETTING
DEFAULT(1) R/W
DESCRIPTION
1.36864.15:7
Reserved
000âh
1.36864.6
1.36864.5
1.36864.4
1.36864.3
1.36864.2
PCS Byte S
RX Power
PMA LF
PCS LF
PCS Code
1 = trigger LASI by
corresponding bit of
1.36867 (1.9003âh)
0 = LASI ignores
corresponding bit of
1.36867 (1.9003âh)
0âb
1âb
1âb
1âb
0âb/1âb
R/W
PCS Byte Sync Fail LASI Enable
R/W
Receive Laser Pwr/Sig Det LASI Enable
R/W
PMA RX Local Fault LASI Enable
R/W
PCS RX Local Fault LASI Enable
R/W
8b/10b Code Violation LASI Enable
1.36864.1
DOM RX
1âb
R/W
DOM RX or RX EFIFO Fault LASI Enable
1.36864.0
PHY RX LF
1âb
R/W
PHY RX Local Fault LASI Enable
Note (1): Where two values are given, Default depends on LX4/CX4 select LX4_MODE pin. First value is LX4 value. The value may be overwritten by the Auto-
Configure operation (See âAuto-Configuring Control Registersâ on page 16 and Table 92 for details).
Table 25. XENPAK LASI TX_ALARM CONTROL REGISTER
MDIO REGISTER, ADDRESS = 1.36865 (1.9001âh)
BIT
NAME
SETTING
DEFAULT(1) R/W
DESCRIPTION
1.36865.15:11
Reserved
000âh
1.36865.10
1.36865.9
1.36865.8
1.36865.7
1.36865.6
PHY S_D
LBC
LTEMP
LOP
TX LF
1 = trigger LASI from
corresponding bit of
1.36868 (1.9004âh)
0 = LASI ignores
corresponding bit of
1.36868 (1.9004âh)
0âb/1âb
1âb/0âb
1âb/0âb
1âb/0âb
1âb/0âb
R/W
PHY XS Signal Detect LASI Enable
R/W
Laser Bias Current Fault LASI Enable
R/W
Laser Temperature Fault LASI Enable
R/W
Laser Output Power Fault LASI Enable
R/W
Transmit Local Fault LASI Enable
1.36865.5
Byte Sync
0âb/1âb
R/W
PHY XS Byte Sync Fail LASI Enable
1.36865.4
PMA LF
1âb
R/W
PMA TX Local Fault LASI Enable
1.36865.3
PCS LF
1âb/0âb
R/W
PCS TX Local Fault LASI Enable
1.36865.2
TX EFIFO
0âb/1âb
R/W
Transmit EFIFO Error LASI Enable
1.36865.1
DOM TX/
PHY Code
1âb
R/W
DOM TX or PHY XS 8b/10b Code Violation Fault LASI
Enable
1.36865.0
PHY TX LF
1âb
R/W
PHY TX Local Fault LASI Enable
Note (1): Where two values are given, Default depends on LX4/CX4 select LX4_MODE pin. First value is LX4 value. The value may be overwritten by the Auto-
Configure operation (See âAuto-Configuring Control Registersâ on page 16 and Table 92 for details).
Table 26. XENPAK LASI CONTROL REGISTER
MDIO REGISTER, ADDRESS = 1.36866 (1.9002âh)
BIT
NAME
SETTING
DEFAULT(1) R/W
DESCRIPTION
1.36866.15:4
1.36866.3
1.36866.2
1.36866.1
Reserved
GPIO
RX_Alarm
TX_Alarm
1 = trigger LASI via bit in
1.36869 (1.9005âh)
0 = LASI ignores bit
000âh
0âb
0âb
0âb
R/W
Enable GPIO pins to trigger LASI(2)
R/W
Enable RX_Alarm to trigger LASI
R/W
Enable TX_Alarm to trigger LASI
1.36866.0
LS_Alarm
0âb
R/W
Enable Link Status change to trigger LASI
Note (1): The default values may be overwritten by the Auto-Configure operation (See âAuto-Configuring Control Registersâ on page 16 and Table 92 for details). Since
on Power up or RESET several LASI contributors will initially be in the âfaultâ condition (in particular, Byte Synch and Lane Alignment, and their derivatives), it
may be advisable for a host to clear these before enabling these to trigger LASI.
Note (2): See description of the General Purpose Input/Output (GPIO) pins and bits for a description of how they contribute to the LASI system.
27
|
▷ |