BBT3821 Datasheet, PDF (38/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
Table 55. OPTICAL STATUS & CONTROL PIN POLARITY REGISTER
MDIO REGISTER ADDRESS = 1.49181 (1.C01D’h)
BIT
NAME
SETTING
DEFAULT⁽¹⁾ R/W
DESCRIPTION
1.49181.15:7
Reserved
1.49181.6
OPRLOS[3:0]
1 = low -> LOS
0’b
0 = high -> LOS
R/W
Input polarity to 1.10 and enable Byte Synch in
LX4 mode
1.49181.5
1.49181.4
TX_ENA[3:0]
1 = Active Low
0’b
TX_ENC
0 = Active Hi
0’b
R/W
Polarity of TX_ENA outputs
R/W
Polarity of TX_ENC input
1.49181.3
1.49181.2
1.49181.1
OPRXOP
OPTTEMP
OPTXLBC
1 = Pin Low to trigger 0’b
LASI
0 = Pin High to trigger
0’b
LASI
0’b
R/W
Control Polarity of respective input pins which
R/W
will trigger LASI (if enabled)
R/W
1.49181.0
OPTXLOP
0’b
R/W
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Table 56. MDIO PCS DEVAD 3 REGISTERS
PCS DEVICE 3 MDIO REGISTERS
ADDRESS
DEC
HEX
NAME
DESCRIPTION
DEFAULT AC⁽²⁾ R/W
DETAILS
3.0
3.1
3.2:3
3.0
3.1
3.2:3
PCS Control 1
PCS Status 1
ID Code
Reset, Enable loop back mode.
PCS Fault, Link Status
Manufacturer and Device OUI
2040’h
0004’h ⁽³⁾
01839C6V’h
R/W
RO LL
RO
Table 57
Table 58
See ⁽¹⁾
3.4
3.4
Speed Ability
10Gbps Ability
0001’h
RO
Table 7
3.5
3.5
IEEE Devices Devices in Package, Clause 22 capable
001A’h
RO
Table 8
3.6
3.6
Vendor Devices Vendor Specific Devices in Pkg
0000’h
RO
Table 8
3.7
3.8
3.14:15
3.24
3.7
3.8
3.E:F
3.18
PCS Type
PCS Status 2
Package ID
PCS-X Status 3
IEEE PCS TYPE SELECT REGISTER
Device Present, Local Fault, Type Summary
Package OUI, etc.
IEEE 10GBASE-X PCS STATUS REGISTER
0001’h
8002’h ⁽³⁾
00000000’h
See ⁽⁵⁾
RO
Table 59
RO
Table 60
RO
See ⁽⁴⁾
RO
Table 61
3.25
3.19
PCS Test
IEEE 10GBASE-X PCS TEST CONTROL
REGISTER
0000’h
R/W
Table 62
3.49152 3.C000 PCS Control 2 PCS CONTROL REGISTER 2
0F6F’h
A
R/W
Table 63
3.49153 3.C001 PCS Control 3 PCS Control Register 3
0801’h
A
R/W
Table 64
3.49154 3.C002 PCS ERROR PCS INTERNAL ERROR CODE REGISTER
00FE’h
A
R/W
Table 66
3.49155 3.C003 PCS IDLE
PCS INTERNAL IDLE CODE REGISTER
0007’h
A
R/W
Table 67
3.49156
3.C004
PCS // Loop Back PCS PARALLEL NETWORK LOOP BACK
CONTROL REGISTER
0000’h
A
R/W
Table 68
3.49159 3.C007 Test_Flags
Receive Path Test & Status Flags
0000’h
RO LH Table 69
3.49160 3.C008 Output Ctrl
Output Control and Test function
AAAA’h
R/W
Table 70
3.49161 3.C009 Half Rate
Half rate clock mode enable
0000’h
R/W
Table 71
3.49164 3.C00C BIST Ctrl
BIST Control Register
0000’h
R/W
Table 72
3.49165
3.49166
3.C00D BIST Error
3.C00E
BIST ERROR Counter Registers
0000’h
RO/
RCNR
Table 73
3.49167 3.C00F Soft Reset
Reset (non MDIO)
0000’h
R/W SC Table 46
Note (1): ‘V’ is a version number. See “JTAG & AC-JTAG Operations” on page 53 for a note about the version number.
Note (2): For rows with “A”, the default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92
for details).
Note (3): Read value depends on status signal values. Value shown indicates ‘normal’ operation.
Note (4): The IEEE 802.3ae specification allows this to be all zeroes. A XENPAK (etc.) host can more readily determine where the NVR registers are if this value is zero.
Note (5): If IEEE 802.3ae (and default) setting for PCS Loopback, 180F’h. If PCS Loopback allowed, 1C0F’h. See Table 61 and Table 64.
38