BBT3821 Datasheet, PDF (45/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

BBT3821
Table 73. BIST ERROR COUNTER REGISTERS
MDIO REGISTER ADDRESSES = 3.49165:6 (3.C00D:E’h)
BIT
3.49165.15:8
3.49165.7:0
3.49166.15:8
3.49166.7:0
NAME
BIST_ERR_CNT_3
BIST_ERR_CNT_2
BIST_ERR_CNT_1
BIST_ERR_CNT_0
SETTING
Lane 3 errors
Lane 2 errors
Lane 1 errors
Lane 0 errors
DEFAULT
00’h
00’h
00’h
00’h
R/W
RCNR⁽¹⁾
RCNR⁽¹⁾
RCNR⁽¹⁾
RCNR⁽¹⁾
DESCRIPTION
Error byte counter of BIST pattern
checker on each Lane
Note (1): The counters do not rollover at FF’h, and are cleared on read. There is also an error flag bit, see register 4.C007, Table 88.
Table 74. MDIO PHY XS DEVAD 4 REGISTERS
PHY XS DEVICE 4 MDIO REGISTERS
ADDRESS
DEC
HEX
NAME
DESCRIPTION
AC
DEFAULT (2)
R/W
DETAILS
4.0
4.1
4.2:3
4.0
4.1
4.2:3
PHYXS Control 1
PHYXS Status 1
ID Code
Reset, Enable loop back mode.
PCS Fault, Link Status
Manufacturer and Device OUI
2040’h
0004’h ⁽³⁾
01839C6V’h
R/W
RO (LL)
RO
Table 75
Table 76
See ⁽¹⁾
4.4
4.4
Speed Ability
10Gbps Ability
0001’h
RO
Table 7
4.5
4.5
IEEE Devices
Devices in Package, Clause 22 capable
001A’h
RO
Table 8
4.6
4.6
Vendor Devices Vendor Specific Devices in Pkg
0000’h
RO
Table 8
4.8
4.8
PHYXS Status 2 Device Present, Local Fault, Type Summary 8000’h ⁽³⁾
RO
Table 77
4.14:15 4.E:F
Package ID
Package OUI, etc.
00000000’h
RO
See ⁽⁴⁾
4.24
4.18
PHYXS Status 3 10GBASE-X PHY XGXS Status
1C0F’h
RO
Table 78
4.25
4.19
PHYXS Test
10GBASE PHY XS Test Control
0000’h
R/W
Table 79
4.49152 4.C000 PHYXS Control 2 PHY XS Control Register 2
0F6F’h
A R/W
Table 80
4.49153 4.C001 PHYXS Control 3 PHY XS Control Register 3
0800’h
A R/W
Table 81
4.49154 4.C002 PHYXS ERR
PHY XS Internal ERROR code register
00FE’h
A R/W
Table 82
4.49155 4.C003 PHYXS IDLE
PHY XS Internal IDLE Code Register
0007’h
A R/W
Table 83
4.49156 4.C004 PHYXS Loop Back PHY XS Loop Back Control Register
0000’h
A R/W
Table 84
4.49157 4.C005 PRE_EMPH
PHY XS Pre-emphasis level
0000’h
A R/W
Table 85
4.49158 4.C006 Equalization
PHY XS Equalization Control
0000’h
A R/W
Table 87
4.49159 4.C007 Test_Flags
PHY XS Receive Path Test & Status Flags 0000’h
RO LH
Table 88
4.49160 4.C008 Output Ctrl
Output Control and Test function
AAAA’h
R/W
Table 89
4.49161 4.C009 Half Rate
Half rate clock mode enable
0000’h
R/W
Table 71
4.49162 4.C00A LOS Det
PHY XS Status 4 LOS Register
0000’h
RO LH
Table 90
4.49163 4.C00B Reserved
PHY XS Control 4 TXCLK20
0000’h
R/W
Table 91
4.49167 4.C00F Soft Reset
Reset (non MDIO)
0000’h
R/W SC
Table 46
Note (1): ‘V’ is a version number. See “JTAG & AC-JTAG Operations” on page 53 for a note about the version number.
Note (2): For rows with “A”, the default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92
for details).
Note (3): Read value depends on status signal values. Value shown indicates ‘normal’ operation.
Note (4): The IEEE 802.3ae spec allows this to be all zeroes. A XENPAK (etc.) host can more readily determine where the NVR registers are if this value is zero.
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