X6800 Datasheet, PDF (92/122 Pages) Intel Corporation – Core2 Extreme Processor

Thermal Specifications and Design Considerations
5.4
Platform Environment Control Interface (PECI)
5.4.1 Introduction
Figure 27.
PECI offers an interface for thermal monitoring of Intel processor and chipset
components. It uses a single wire, thus alleviating routing congestion issues. Figure 27
shows an example of the PECI topology in a system. PECI uses CRC checking on the
host side to ensure reliable transfers between the host and client devices. Also, data
transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to
2 Mbps). The PECI interface on the processor is disabled by default and must be
enabled through BIOS.
Processor PECI Topology
PECI Host
Controller
Land G5
Domain 0
5.4.1.1
Key Difference with Legacy Diode-Based Thermal Management
Fan speed control solutions based on PECI uses a T_CONTROL value stored in the
processor IA32_TEMPERATURE_TARGET MSR. The T_CONTROL MSR uses the same offset
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the T_CONTROL value as negative. Thermal management algorithms
should use the relative temperature value delivered over PECI in conjunction with the
T_CONTROL MSR value to control or optimize fan speeds. Figure 28 shows a conceptual
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
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Datasheet