X6800 Datasheet, PDF (30/122 Pages) Intel Corporation – Core2 Extreme Processor

Electrical Specifications
.
Table 14.
2.7.3.1
Table 15.
CMOS Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes¹
V_IL
Input Low Voltage
-0.10
V_TT * 0.30 V
2, 3
V_IH Input High Voltage
V_TT * 0.70 V_TT + 0.10 V
3, 4, 5
V_OL Output Low Voltage
-0.10
V_TT * 0.10 V
3
V_OH Output High Voltage
0.90 * V_TT V_TT + 0.10 V
3, 6, 5
I_OL
Output Low Current
1.70
4.70
mA
3, 7
I_OH Output High Current
1.70
4.70
mA
3, 7
I_LI
Input Leakage Current
N/A
± 100
µA
8
I_LO
Output Leakage Current
N/A
± 100
µA
9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V_IL is defined as the voltage range at a receiving agent that will be interpreted as a logical low
value.
3. The V_TT referred to in these specifications refers to instantaneous V_TT.
4. V_IH is defined as the voltage range at a receiving agent that will be interpreted as a logical high
value.
5. V_IH and V_OH may experience excursions above V_TT.
6. All outputs are open drain.
7. I_OL is measured at 0.10 * V_TT. I_OH is measured at 0.90 * V_TT.
8. Leakage to V_SS with land held at V_TT.
9. Leakage to V_TT with land held at 300 mV.
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 10 for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 15 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
GTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units Notes¹
GTLREF_PU GTLREF pull up resistor
124 * 0.99 124 124 * 1.01 Ω
2
GTLREF_PD GTLREF pull down resistor 210 * 0.99 210 210 * 1.01 Ω
2
R_TT
Termination Resistance
COMP[3:0] COMP Resistance
45
50
55
Ω
3
49.40
49.90
50.40
Ω
4
COMP8
COMP Resistance
24.65
24.90
25.15
Ω
4
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. GTLREF is to be generated from V_TT by a voltage divider of 1% resistors (one divider for each
GTLEREF land).
3. R_TT is the on-die termination resistance measured at V_TT/3 of the GTL+ output driver.
4. COMP resistance must be provided on the system board with 1% resistors. See the applicable
platform design guide for implementation details. COMP[3:0] and COMP8 resistors are tied to
V_SS.
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Datasheet