X6800 Datasheet, PDF (28/122 Pages) Intel Corporation – Core2 Extreme Processor

Electrical Specifications
.
Table 10.
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Table 11.
2.7.2
Signal Characteristics
Signals with R_TT
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
Open Drain Signals¹
Signals with No R_TT
A20M#, BCLK[1:0], BSEL[2:0],
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#, TESTHI[13:0],
VID[6:1], GTLREF[1:0], TCK, TDI, TMS,
TRST#, VTT_SEL, MSID[1:0]
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, FCx
NOTES:
1. Signals that do not have R_TT, nor are actively driven to their high-voltage level.
Signal Reference Voltages
GTLREF
V_TT/2
BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
PWRGOOD¹, SMI#, STPCLK#, TCK¹,
TDI¹, TMS¹, TRST#¹
NOTES:
1. These signals also have hysteresis added to the reference voltage. See Table 13 for more
information.
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-
asserted for at least four BCLKs in order for the processor to recognize the proper
signal state. See Section 2.7.3 for the DC. See Section 6.2 for additional timing
requirements for entering and leaving the low power states.
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Datasheet