X6800 Datasheet, PDF (74/122 Pages) Intel Corporation – Core2 Extreme Processor

Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 1 of 9)
Name
Type
Description
HIT#
HITM#
IERR#
IGNNE#
INIT#
ITP_CLK[1:0]
LINT[1:0]
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Any FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can
be continued by reasserting HIT# and HITM# together.
Output
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#.
This signal does not have on-die termination. Refer to Section 2.6.2
for termination requirements.
Input
IGNNE# (Ignore Numeric Error) is asserted to the processor to
ignore a numeric error and continue to execute noncontrol floating-
point instructions. If IGNNE# is de-asserted, the processor
generates an exception on a noncontrol floating-point instruction if
a previous floating-point instruction caused an error. IGNNE# has
no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
Input
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the
appropriate pins/lands of all processor FSB agents.
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in
the system, ITP_CLK[1:0] are no connects in the system. These are
not processor signals.
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate
pins/lands of all APIC Bus agents. When the APIC is disabled, the
LINT0 signal becomes INTR, a maskable interrupt request signal,
and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI
are backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default
configuration.
74
Datasheet