X6800 Datasheet, PDF (35/122 Pages) Intel Corporation – Core2 Extreme Processor

Electrical Specifications
2.8
Table 20.
PECI DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors (may also include chipset components in the future) and
external thermal monitoring devices. The processor contains Digital Thermal Sensors
(DTS) distributed throughout die. These sensors are implemented as analog-to-digital
converters calibrated at the factory for reasonable accuracy to provide a digital
representation of relative processor temperature. PECI provides an interface to relay
the highest DTS temperature within a die to external management devices for thermal/
fan speed control. More detailed information is available in the Platform Environment
Control Interface (PECI) Specification.
PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units Notes¹
V_in
V_hysteresis
Input Voltage Range
Hysteresis
-0.15
V_TT
0.1 * V_TT
—
V
V
2
V_n
Negative-edge threshold voltage
0.275 * V_TT 0.500 * V_TT
V
V_p
Positive-edge threshold voltage
0.550 * V_TT 0.725 * V_TT
V
I_source
High level output source
(V_OH = 0.75 * V_TT)
-6.0
N/A
mA
Low level output sink
I_sink
(V_OL = 0.25 * V_TT)
0.5
I_leak+
High impedance state leakage to V_TT
N/A
I_leak-
High impedance leakage to GND
N/A
C_bus
Bus capacitance per node
N/A
1.0
mA
50
µA
3
10
µA
3
10
pF
4
V_noise
Signal noise immunity above 300 MHz
0.1 * V_TT
—
V_p-p
NOTES:
1. V_TT supplies the PECI interface. PECI behavior does not affect V_TT min/max specifications. Refer
to Table 4 for V_TT specifications.
2. The input buffers use a Schmitt-triggered input design for improved noise immunity.
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths
might appear as additional nodes.
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Datasheet
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