JA80386EXTC25 Datasheet, PDF (53/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Figure 26. Halt Cycle
Cycle 1
Cycle 2
Idle
Nonpipelined Nonpipelined
(Write)
(Halt)
[Late Ready]
T1 T2 T1 T2 Ti
Ti
Ti
Ti
CLK2
CLKOUT
BHE#, A1, M/IO#, W/R#
A25:2, BLE#, D/C#
WR#
Valid 1
Valid 1
CPU remains halted until INTR, SMI#,
NMI, or RESET is asserted.
CPU responds to HOLD input
while in the HALT state.
RD#
ADS#
NA#
READY#
†
LBA#
LOCK#
D15:0
Valid 1
Out
Valid 2
Undefined
Float
† HALT cycle must be acknowledged by READY# asserted. This READY# could be
generated internally or externally.
A2492-02
Datasheet
53