JA80386EXTC25 Datasheet, PDF (47/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
7.0
Bus Cycle Waveforms
Figures 20 through 30 present various bus cycles that are generated by the processor. What is
shown in the figure is the relationship of the various bus signals to CLK2. These figures along with
the information present in AC Specifications allow the user to determine critical timing analysis for
a given application.
Figure 20. Basic Internal and External Bus Cycles
Idle
Cycle
Cycle 1
Nonpipelined
External
(Write)
[Late Ready]
Cycle 2
Nonpipelined
Internal
(Read)
Cycle 3
Nonpipelined
Internal
(Write)
[Early Ready]
Idle
Cycle
Cycle 4
Nonpipelined
External
(Read)
Idle
Cycle
State ^{Ti T1 T2 T1 T2 T1 T2 Ti T1 T2 Ti}
CLK2
CLKOUT
A25:1, BHE#
BLE#, D/C#
M/IO#
REFRESH#
Valid 1
Valid 2
Valid 3
Valid 4
W/R#
WR#
RD#
ADS#
NA#
READY#
LBA#
BS8#
LOCK#
D15:0
End Cycle 1 End Cycle 2 End Cycle 3
End Cycle 4
Valid 1
Out 1
Valid 2
In
2
Valid 3
Out 3
Valid 4
In
4
A2486-03
Datasheet
47