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JA80386EXTC25 Datasheet, PDF (37/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor
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Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 1 of 5)
Symbol
Parameter
25 MHz
3.0 V to 3.6 V
Min.
(ns)
Max.
(ns)
20 MHz
2.7 V to 3.6 V
Min.
(ns)
Max.
(ns)
Test Condition
Operating Frequency
0
25
0
20
one-half CLK2 frequency
in MHz(1)
t1
CLK2 Period
20
25
t2a
CLK2 High Time
7
8
(2)
t2b
CLK2 High Time
4
5
(2)
t3a
CLK2 Low Time
7
8
(2)
t3b
CLK2 Low Time
5
6
(2)
t4
CLK2 Fall Time
7
8 (2)
t5
CLK2 Rise Time
7
8 (2)
t6
A25:1 Valid Delay
4
32
4
36 CL = 50 pF
t7
A25:1 Float Delay
4
29
4
36 (3)
t8
BHE#, BLE#, LOCK# Valid
Delay
4
32
4
34 CL = 50 pF
t8a
SMIACT# Valid Delay
4
32
4
34 CL = 50 pF
t9
BHE#, BLE#, LOCK# Float
Delay
4
23
4
32 (3)
t10
M/IO#, D/C#, W/R#, ADS#,
REFRESH# Valid Delay
4
32
4
34 CL = 50 pF
t10a
RD#, WR# Valid Delay
4
30
4
32
WR# Valid Delay for the rising
t10b
edge with respect to phase
4
37
4
37 (6)
two (external late READY#)
M/IO#, D/C#, W/R#,
t11
REFRESH#, ADS# Float
Delay
4
30
4
34 (3)
t12
D15:0 Write Data Valid Delay
4
31
4
34 CL = 50 pF
t13
D15:0 Write Data Float delay
4
20
4
28 (3)
t14
HLDA Valid Delay
4
30
4
32 CL = 50 pF
t15
NA# Setup Time
9
9
t16
NA# Hold Time
12
15
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
Datasheet
37
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