JA80386EXTC25 Datasheet, PDF (33/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 2 of 5)
Symbol
Parameter
33 MHz
Min.
(ns)
Max.
(ns)
25 MHz
Min.
(ns)
Max.
(ns)
Test Condition
t₂₀
READY#, BS8# Hold Time
4
t₂₁
D15:0 Read Setup Time
7
t₂₂
D15:0 Read Hold Time
4
t₂₃
HOLD Setup Time
8
t₂₄
HOLD Hold Time
3
t₂₅
RESET Setup Time
5
t₂₆
RESET Hold Time
2
t₂₇
NMI Setup Time
6
t_27a
SMI# Setup Time
6
t₂₈
NMI Hold Time
6
t_28a
SMI# Hold Time
6
t₂₉
PEREQ, ERROR#, BUSY# Setup
Time
6
4
7
4
8
3
5
3
6
(4)
6
(4)
6
(4)
6
(4)
6
(4)
t₃₀
PEREQ, ERROR#, BUSY# Hold
Time
5
5
(4)
t₃₁
READY# Valid Delay
t₃₂
READY# Float Delay
t₃₃
LBA# Valid Delay
t₃₄
CS6:0#, UCS# Valid Delay
4
24
4
4
34
4
4
20
4
4
24 (25 in
SMM)
4
26 C_L = 30 pF
34
22
30 C_L = 30 pF
t₃₅
CLKOUT Valid Delay
2
9
2
14 C_L = 30 pF
t₃₆
PWRDOWN Valid Delay
4
15
4
18
t₄₁
A25:1, BHE#, BLE# Valid to WR#
Low
0
0
t_41a
UCS#, CS6:0# Valid to WR# Low
0
t₄₂
A25:1, BHE#, BLE# Hold After
WR# High
0
0
0
(6)
t_42a
UCS#, CS6:0# Hold after WR#
High
0
0
t_42b
A25:1. BHE#, BLE# Hold After
WR# High
10
10
(7, 8)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I_LO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
Datasheet
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