JA80386EXTC25 Datasheet, PDF (13/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 1 of 6)
Symbol
Type Output States
Name and Function
A25:1
H(Z)
Address Bus outputs physical memory or port I/O addresses.
O
R(1)
I(1)
These signals are valid when ADS# is active and remain valid
until the next T1, T2P, or Ti. During HOLD cycles they are driven
P(1)
to a high-impedance state. A18:16 are multiplexed with CAS2:0.
ADS#
O
H(Z)
R(1)
I(1)
P(1)
Address Status indicates that the processor is driving a valid
bus-cycle definition and address (W/R#, D/C#, M/IO#, A25:1,
BHE#, BLE#) onto its pins.
BHE#
H(Z)
O
R(0)
I(X)
Byte High Enable indicates that the processor is transferring a
high data byte.
P(0)
BLE#
H(Z)
O
R(0)
I(X)
Byte Low Enable indicates that the processor is transferring a
low data byte.
P(1)
BS8#
I
Bus Size indicates that an 8-bit device is currently being
addressed.
BUSY#
I
Busy indicates that the math coprocessor is busy. If BUSY# is
sampled LOW at the falling edge of RESET, the processor
performs an internal self test. BUSY# is multiplexed with
TMRGATE2 and has a temporary weak pull-up resistor.
CAS2:0
O
H(Z)
R(1)
I(1)
P(1)
Cascade Address carries the slave address information from
the 8259A master interrupt module during interrupt acknowledge
bus cycles. CAS2:0 are multiplexed with A18:16.
CLK2
ST
Clock Input is connected to an external clock that provides the
fundamental timing for the device.
H(Q)
CLKOUT
O
R(Q)
I(Q)
CLKOUT is a PH1P clock output.
P(0)
COMCLK
I
Serial Communications Baud Clock is an alternate clock
source for the asynchronous serial ports. COMCLK is
multiplexed with P3.7 and has a temporary weak pull-down
resistor.
CS4:0#
H(1)
Chip-selects are activated when the address of a memory or I/O
O
R(WH)
I(Q)
bus cycle is within the address region programmed by the user.
They are multiplexed as follows: CS6# with REFRESH#, CS5#
P(X)
with DACK0#, and CS4:0# with P2.4:0.
CS6:5#
H(1)
Chip-selects are activated when the address of a memory or I/O
O
R(1)
I(Q)
bus cycle is within the address region programmed by the user.
They are multiplexed as follows: CS6# with REFRESH#, CS5#
P(X)
with DACK0#, and CS4:0# with P2.4:0.
CTS1:0#
I
Clear to Send SIO1 and SIO0 prevent the transmission of data
to the asynchronous serial port’s RXD1 and RXD0 pins,
respectively. CTS1# is multiplexed with EOP#, and CTS0# is
multiplexed with P2.7. CTS1# requires an external pull-up
resistor. Both have temporary weak pull-up resistors.
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Datasheet
13