JA80386EXTC25 Datasheet, PDF (41/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 5 of 5)
Symbol
Parameter
25 MHz
3.0 V to 3.6 V
Min.
(ns)
Max.
(ns)
20 MHz
2.7 V to 3.6 V
Min.
(ns)
Max.
(ns)
Test Condition
Interrupt Control Unit (ICU) Inputs
t₁₁₅
D7:0 Setup Time
(INTA# Cycle 2)
9
11
t₁₁₆
D7:0 Hold Time
(INTA# Cycle 2)
6
6
Interrupt Control Unit (ICU) Outputs
t₁₁₇
CLK2 High to CAS2:0 Valid
36
46
DMA Unit Inputs
DREQ Setup Time
t₁₁₈
(Sync Mode)
19
21
DREQ Hold Time
t₁₁₉
(Sync Mode)
4
4
(2)
DREQ Setup Time
t₁₂₀
(Async Mode)
11
11
DREQ Hold Time
t₁₂₁
(Async Mode)
11
11
(2)
EOP# Setup Time
t₁₂₂
(Sync Mode)
17
21
EOP# Hold Time
t₁₂₃
(Sync Mode)
4
4
EOP# Setup Time
t₁₂₄
(Async Mode)
11
11
EOP# Hold Time
t₁₂₅
(Async Mode)
11
11
DMA Unit Outputs
t₁₂₆
DACK# Output Valid Delay
4
31
4
33
t₁₂₇
EOP# Active Delay
4
27
4
33
t₁₂₈
EOP# Float Delay
4
27
4
33 (3)
JTAG Test-logic Unit
t₁₂₉
TCK Frequency
10
10 (Unit is MHz)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I_LO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
Datasheet
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