JA80386EXTC25 Datasheet, PDF (17/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 5 of 6)
Symbol
Type Output States
Name and Function
SRXCLK
H(Q)
I/O
R(WH)
I(Q)
SSIO Receive Clock synchronizes data being accepted by the
synchronous serial port. SRXCLK is multiplexed with DTR1#.
P(X)/P(Q)^{Note 1}
SSIORX
I
SSIO Receive Serial Data accepts serial data (most-significant
bit first) being sent to the synchronous serial port. SSIORX is
multiplexed with RI1#.
SSIOTX
SSIO Transmit Serial Data sends serial data (most-significant
H(Q)
bit first) from the synchronous serial port. SSIOTX is multiplexed
O
R(WL)
I(Q)
with RTS1#.
Intel does not specify a data hold time for SSIOTX. Slower
P(X)/P(Q)^{Note 1} _{external devices may require additional hardware to properly}
interface the SSIO unit.
STXCLK
H(Q)
I/O
R(WH)
I(Q)
SSIO Transmit Clock synchronizes data being sent by the
synchronous serial port. STXCLK is multiplexed with DSR1.
P(X)/P(Q)^{Note 1}
TCK
I
TAP (Test Access Port) Controller Clock provides the clock
input for the JTAG logic. It has a permanent weak pull-up
resistor.
TDI
TDO
TAP (Test Access Port) Controller Data Input is the serial
I
input for test instructions and data. It has a permanent weak pull-
up resistor.
H(Z)/H(Q)^{Note 2}
O
R(Z)/R(Q)^{Note 2} TAP (Test Access Port) Controller Data Output is the serial
I(Z)/I(Q)^{Note 2} output for test instructions and data.
P(Z)/ P(Q)^{Note 2}
TMRCLK2:0
I
Timer/Counter Clock Inputs can serve as external clock inputs
for the corresponding timer/counters. (The timer/counters can
also be clocked internally.) They are multiplexed as follows:
TMRCLK2 with PEREQ, TMRCLK1 with INT6, and TMRCLK0
with INT4. TMRCLK2 has a temporary weak pull-down resistor.
TMRGATE2:0
I
Timer/Counter Gate Inputs can control the corresponding
timer/counter’s counting (enable, disable, or trigger, depending
on the programmed mode). They are multiplexed as follows:
TMRGATE2 with BUSY#, TMRGATE1 with INT7, and
TMRGATE0 with INT5. TMRGATE2 has a temporary weak pull-
up resistor.
TMROUT2
O
H(Q)
R(WH)
I(Q)
P(X)/P(Q)^{Note 1}
Timer/Counter Outputs provide the output of the corresponding
timer/counter. The form of the output depends on the
programmed mode. They are multiplexed as follows: TMROUT2
with ERROR#, TMROUT1 with P3.1 and INT8, and TMROUT0
with P3.0 and INT9.
TMROUT1:0
O
H(Q)
R(WL)
I(Q)
P(X)/P(Q)^{Note 1}
Timer/Counter Outputs provide the output of the corresponding
timer/counter. The form of the output depends on the
programmed mode. They are multiplexed as follows: TMROUT2
with ERROR#, TMROUT1 with P3.1 and INT8, and TMROUT0
with P3.0 and INT9.
TMS
I
TAP (Test Access Port) Controller Mode Select controls the
sequence of the TAP controller’s states. It has a permanent
weak pull-up resistor.
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Datasheet
17