JA80386EXTC25 Datasheet, PDF (39/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 3 of 5)
Symbol
Parameter
25 MHz
3.0 V to 3.6 V
Min.
(ns)
Max.
(ns)
20 MHz
2.7 V to 3.6 V
Min.
(ns)
Max.
(ns)
Test Condition
t_42a
UCS#, CS6:0# Hold after
WR# High
0
0
t_42b
A25:1. BHE#, BLE# Hold
After WR# High
10
10
(7, 8)
t₄₃
D15:0 Output Valid to WR#
High
2CLK2
– 10
2CLK2
– 10
(5)
t₄₄
D15:0 Output Hold After WR# CLK2
High
–10
CLK2
–10
t₄₅
WR# High to D15:0 Float
CLK2
+ 10
CLK2
+10
(3)
t₄₆
WR# Pulse Width
2CLK2
–10
2CLK2
–10
(7)
t₄₇
A25:1, BHE#, BLE# Valid to
D15:0 Valid
4CLK2-
41
4CLK2
- 45
(5)
t_47a
UCS#, CS6:0# Valid to D15-
D0 Valid
4CLK2 -
42
4CLK2
- 53
(5)
t₄₈
RD# Low to D15:0 Input Valid
t₄₉
D15:0 Hold After RD# High
t₅₀
RD# High to D15:0 Float
t₅₁
A25:1, BHE#, BLE# Hold
After RD# High
t_51a
UCS#, CS6:0# Hold after
RD# High
t₅₂
RD# Pulse Width
Synchronous Serial I/O (SSIO) Unit
t₁₀₀
STXCLK, SRXCLK
Frequency (Master Mode)
0
0
0
3CLK2
–13
3CLK2 –
39
CLK2
CLK2/8
0
0
0
3CLK2
–15
3CLK2
– 43
(5)
CLK2 (3)
CLK2/8 (Unit is MHz)
t₁₀₁
STXCLK, SRXCLK
Frequency (Slave Mode)
CLK2/8
CLK2/8 (Unit is MHz)
t₁₀₂
STXCLK, SRXCLK Low Time
7CLK2/
2
7CLK2/
2
(2)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I_LO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
Datasheet
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