JA80386EXTC25 Datasheet, PDF (15/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 3 of 6)
Symbol
Type Output States
Name and Function
INT9:0
I
Interrupt Requests are maskable inputs that cause the CPU to
suspend execution of the current program and then execute an
interrupt acknowledge cycle. They are multiplexed as follows:
INT9 with TMROUT0 and P3.0, INT8 with TMROUT1 and P3.1,
INT7 with TMRGATE1, INT6 with TMRCLK1, INT5 with
TMRGATE0, INT4 with TMRCLK0, and INT3:0 with P3.5:2.
INT9, INT8, and INT3:0 have temporary weak pull-down
resistors.
LBA#
H(1)
Local Bus Access is asserted whenever the processor provides
O
R(1)
I(Q)
the READY# signal to terminate a bus transaction. This occurs
when an internal peripheral address is accessed or when the
P(X)
chip-select unit provides the READY# signal.
LOCK#
H(Z)
Bus Lock prevents other bus masters from gaining control of the
O
R(WH)
I(X)
system bus.
P(X)
LOCK# is multiplexed with P1.5.
M/IO#
O
H(Z)
R(0)
I(1)
P(1)
Memory/IO Indicates whether the current bus cycle is a memory
cycle or an I/O cycle. When M/IO# is HIGH, the bus cycle is a
memory cycle; when M/IO# is LOW, the bus cycle is an I/O cycle.
NA#
I
Next Address requests address pipelining.
NMI
ST
Nonmaskable Interrupt Request is a non-maskable input that
causes the CPU to suspend execution of the current program
and execute an interrupt acknowledge cycle.
PEREQ
I
Processor Extension Request indicates that the math
coprocessor has data to transfer to the processor. PEREQ is
multiplexed with TMRCLK2 and has a temporary weak pull-down
resistor.
P1.5:0
H(X)
Port 1, Pins 7:0 are multipurpose bidirectional port pins. They
I/O
R(WH)
I(X)
are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD,
P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with
P(X)
DTR0#, P1.1 with RTS0#, and P1.0 with DCD0#.
P1.7:6
H(X)
Port 1, Pins 7:0 are multipurpose bidirectional port pins. They
I/O
R(WL)
I(X)
are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD,
P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with
P(X)
DTR0#, P1.1 with RTS0#, and P1.0 with DCD0#.
P2.7,4:0
I/O
H(X)
R(WH)
I(X)
P(X)
Port 2, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0,
P2.5 with RXD0, and P2.4:0 with CS4:0#.
P2.6:5
I/O
H(X)
R(WL)
I(X)
P(X)
Port 2, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0,
P2.5 with RXD0, and P2.4:0 with CS4:0#.
P3.7:0
H(X)
Port 3, Pins 7:0 are multipurpose bidirectional port pins. They
I/O
R(WL)
I(X)
are multiplexed as follows: P3.7 with COMCLK, P3.6 with
PWRDOWN, P3.5:2 with INT3:0, and P3.1:0 with TMROUT1:0
P(X)
and INT8:9.
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Datasheet
15