JA80386EXTC25 Datasheet, PDF (34/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 3 of 5)
Symbol
Parameter
33 MHz
Min.
(ns)
Max.
(ns)
25 MHz
Min.
(ns)
Max.
(ns)
Test Condition
t₄₃
D15:0 Output Valid to WR# High
2CLK2
–10
2CLK2
– 10
(5)
t₄₄
D15:0 Output Hold After WR# High
CLK2
–10
CLK2
–10
t₄₅
WR# High to D15:0 Float
CLK2
+ 10
CLK2
(3)
+ 10
t₄₆
WR# Pulse Width
2CLK2
–10
2CLK2
–10
(7)
t₄₇
A25:1, BHE#, BLE# Valid to D15:0
Valid
4CLK2 -
28
4CLK2-
31
(5)
t_47a
UCS#, CS6:0# Valid to D15-D0
Valid
4CLK2 -
31
4CLK2 -
35
(5)
t₄₈
RD# Low to D15:0 Input Valid
3CLK2 –
25
3CLK2 –
29
(5)
t₄₉
D15:0 Hold After RD# High
t₅₀
RD# High to D15:0 Float
t₅₁
A25:1, BHE#, BLE# Hold After
RD# High
0
0
CLK2
CLK2 (3)
0
0
t_51a
UCS#, CS6:0# Hold after RD#
High
0
0
t₅₂
RD# Pulse Width
3CLK2
–10
3CLK2
–10
Synchronous Serial I/O (SSIO) Unit
t₁₀₀
STXCLK, SRXCLK Frequency
(Master Mode)
CLK2/8
CLK2/8 (Unit is MHz)
t₁₀₁
STXCLK, SRXCLK Frequency
(Slave Mode)
CLK2/8
CLK2/8 (Unit is MHz)
t₁₀₂
STXCLK, SRXCLK Low Time
7CLK2/2
7CLK2/2
(2)
t₁₀₃
STXCLK, SRXCLK High Time
7CLK2/2
7CLK2/2
(2)
t₁₀₄
STXCLK Low to SSIOTX Delay
3CLK2
3CLK2
t₁₀₅
SSIORX to SRXCLK High Setup
Time
0
0
(2)
t₁₀₆
SSIORX from SRXCLK Hold Time 3CLK2
3CLK2
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I_LO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
34
Datasheet