JA80386EXTC25 Datasheet, PDF (49/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Figure 22. Pipelined Address Cycle
CLK2
Cycle 1
Pipelined
(Write)
[Late Ready]
T1P T2P T2P
Cycle 2
Non-pipelined
(Read)
T1P T2 T2P
Cycle 3
Pipelined
(Write)
[Late Ready]
T1P T2i T2P
Cycle 4
Pipelined
(Read)
T1P T2
CLKOUT
BHE#, BLE#, A25:1,
M/IO#, D/C#
Valid1
Valid2
Valid3
Valid4
W/R#
WR#
RD#
ADS#
Note ADS# is
asserted in
every T2P state.
NA#
Asserting NA# more
than once during
any cycle has no
additional effects
READY#
LBA#
BS8#
LOCK#
Valid 1
D15:0 Out
Out 1
Valid 2
ADS# is asserted as
soon as the CPU has
another bus cycle to
perform, which is not
always immediately
after NA# is asserted.
As long as the CPU enters the T2P
state during Cycle 3, address
pipelining is maintained in Cycle 4.
NA# could have been asserted in T1P
if desired. Assertion now is the latest
time possible to allow the CPU to enter
T2P state to maintain pipelining in cycle 3.
Valid 3
In
2
Out 3
Valid 4
A2477-03
Datasheet
49