JA80386EXTC25 Datasheet, PDF (16/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 4 of 6)
Symbol
Type Output States
Name and Function
PWRDOWN
O
RD#
O
READY#
I/O
H(Q)
R(WL)
I(X)
P(1)
H(1)
R(1)
I(1)
P(1)
H(Z)
R(Z)
I(Z)
P(Z)
Powerdown indicates that the processor is in powerdown mode.
PWRDOWN is multiplexed with P3.6.
Read Enable indicates that the current bus cycle is a read cycle.
Ready indicates that the current bus transaction has completed.
An external device or an internal signal can drive READY#.
Internally, the chip-select wait-state logic can generate the ready
signal and drive the READY# pin active.
RESET
ST
Reset suspends any operation in progress and places the
processor into a known reset state.
REFRESH#
O
H(1)
R(1)
I(Q)
P(X)
Refresh indicates that the current bus cycle is a refresh cycle.
REFRESH# is multiplexed with CS6#.
RI1:0#
I
Ring Indicator SIO1 and SIO0 indicate that the modem or data
set has received a telephone ringing signal. RI1# is multiplexed
with SSIORX, and RI0# is multiplexed with P1.4 and has a
temporary weak pull-up resistor.
RTS1#
H(X)
Request-to-send SIO1 and SIO0 indicate that corresponding
O
R(WL)
I(X)
asynchronous serial channel is ready to exchange data with the
modem or data set. RTS1# is multiplexed with SSIOTX, and
P(X)
RTS0# is multiplexed with P1.1.
RTS0#
H(X)
Request-to-send SIO1 and SIO0 indicate that corresponding
O
R(WH)
I(X)
asynchronous serial channel is ready to exchange data with the
modem or data set. RTS1# is multiplexed with SSIOTX, and
P(X)
RTS0# is multiplexed with P1.1.
RXD1:0
I
Receive Data SIO1 and SIO0 accept serial data from the
modem or data set to the corresponding asynchronous serial
channel. RXD1 is multiplexed with DRQ1, and RXD0 is
multiplexed with P2.5 and has a temporary weak pull-down
resistor.
SMI#
ST
System Management Interrupt invokes System Management
Mode (SMM). SMI# is the highest priority external interrupt. It is
latched on its falling edge and forces the CPU into SMM upon
completion of the current instruction. SMI# is recognized on an
instruction boundary and at each iteration for repeat string
instructions. SMI# cannot interrupt LOCKed bus cycles or a
currently executing SMM. When the processor receives a
second SMI# while in SMM, it latches the second SMI# on the
SMI# falling edge. However, the processor must exit SMM by
executing a resume instruction (RSM) before it can service the
second SMI#. SMI# has a permanent weak pull-up resistor.
SMIACT#
O
H(1)
R(1)
I(X)
P(X)
System Management Interrupt Active indicates that the
processor is operating in System Management Mode (SMM). It
is asserted when the processor initiates an SMM sequence and
remains asserted (LOW) until the processor executes the
resume instruction (RSM).
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
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