JA80386EXTC25 Datasheet, PDF (38/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 2 of 5)
Symbol
Parameter
25 MHz
3.0 V to 3.6 V
Min.
(ns)
Max.
(ns)
20 MHz
2.7 V to 3.6 V
Min.
(ns)
Max.
(ns)
Test Condition
t₁₉
READY# Setup Time
15
17
t_19a
BS8# Setup Time
17
19
t₂₀
READY#, BS8# Hold Time
4
4
t₂₁
D15:0 Read Setup Time
9
11
t₂₂
D15:0 Read Hold Time
6
6
t₂₃
HOLD Setup Time
17
22
t₂₄
HOLD Hold Time
5
5
t₂₅
RESET Setup Time
12
13
t₂₆
RESET Hold Time
4
4
t₂₇
NMI Setup Time
16
16
t_27a
SMI# Setup Time
16
16
t₂₈
NMI Hold Time
16
16
t_28a
SMI# Hold Time
16
16
t₂₉
PEREQ, ERROR#, BUSY#
Setup Time
14
16
t₃₀
PEREQ, ERROR#, BUSY#
Hold Time
5
5
t₃₁
READY# Valid Delay
t₃₂
READY# Float Delay
t₃₃
LBA# Valid Delay
t₃₄
CS6:0#, UCS# Valid Delay
4
33
4
4
33
4
4
31
4
4
33 (34 in
SMM)
4
t₃₅
CLKOUT Valid Delay
4
14
4
t₃₆
PWRDOWN Valid Delay
4
26
4
t₄₁
A25:1, BHE#, BLE# Valid to
WR# Low
0
0
(4)
(4)
(4)
(4)
(4)
(4)
42 C_L = 30 pF
42
40
42 C_L = 30 pF
18 C_L = 30 pF
29
t_41a
UCS#, CS6:0# Valid to WR#
Low
0
0
t₄₂
A25:1, BHE#, BLE# Hold
After WR# High
0
0
(6)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I_LO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
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Datasheet