JA80386EXTC25 Datasheet, PDF (40/56 Pages) Intel Corporation – Intel386™ EX Embedded Microprocessor

Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 4 of 5)
Symbol
Parameter
25 MHz
3.0 V to 3.6 V
Min.
(ns)
Max.
(ns)
20 MHz
2.7 V to 3.6 V
Min.
(ns)
Max.
(ns)
Test Condition
t₁₀₃
STXCLK, SRXCLK High Time
7CLK2/
2
7CLK2/
2
(2)
t₁₀₄
STXCLK Low to SSIOTX
Delay
3CLK2
3CLK2
t₁₀₅
SSIORX to SRXCLK High
Setup Time
0
0
(2)
t₁₀₆
SSIORX from SRXCLK Hold
Time
3CLK2
3CLK2
Timer Control Unit (TCU) Inputs
t₁₀₇
TMRCLKn Frequency
t₁₀₈
TMRCLKn Low
t₁₀₉
TMRCLKn High
t₁₁₀
TMRGATEn High Width
t₁₁₁
TMRGATEn Low Width
TMRGATEn to TMRCLK
t₁₁₂
Setup Time (external
TMRCLK only)
8
8 (Unit is MHz)
60
60
60
60
50
50
50
50
10
15
t_112a
TMRGATEn to TMRCLK Hold
Time (external TMRCLK only)
19
19
Timer Control Unit (TCU) Outputs
t₁₁₃
TMRGATEn Low to TMROUT
Valid
44
52
t₁₁₄
TMRCLKn Low to TMROUT
Valid
48
52
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I_LO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
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Datasheet