HYB25D256800CT Datasheet, PDF (9/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

256 Mbit Double-Data-Rate SDRAM
DDR SDRAM
HYB25D256[40/80/16]0CE(L)
HYB25D256[40/80/16]0C[T/C/F]
1
Overview
1.1
Features
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 1.5 (DDR200 only), 2, 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• RAS-lockout supported t_RAP=t_RCD
• 7.8 µs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
• V_DDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); V_DDQ = 2.6 V ± 0.1 V (DDR400)
• V_DD = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); V_DD = 2.6 V ± 0.1 V (DDR400)
• P-TFBGA-60-12 package with 3 depopulated rows (8 × 12 mm²)
• P-TSOPII-66 package
• Lead- and halogene-free = green product
Table 1 Performance
Part Number Speed Code
–5
Speed Grade
Component
DDR400B
Module
PC3200-3033
max. Clock Frequency
@CL3
@CL2.5
@CL2
f_CK3 200
f_CK2.5 166
f_CK2 133
–6
DDR333
PC2700–2533
166
166
133
–7
DDR266A
PC2100-2033
—
143
133
Unit
—
—
MHz
MHz
MHz
Data Sheet
9
Rev. 1.6, 2004-12