HYB25D256800CT Datasheet, PDF (13/94 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Pin Configuration
Table 4 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
K7, 29
A0
I
SSTL Address Bus 11:0
L8, 30
L7, 31
M8, 32
M2, 35
L3, 36
L2, 37
K3, 38
K2, 39
A1
I
A2
I
A3
I
A4
I
A5
I
A6
I
A7
I
A8
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Note: Provide the row address for Active commands, and the
column address and Auto Precharge bit for Read/Write
commands, to select one location out of the memory array
in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to
one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0, BA1.
The address inputs also provide the op-code during a Mode
Register Set command.
J3, 40
A9
I
SSTL
K8, 28
A10
I
SSTL
AP
I
SSTL
J2, 41
A11
I
SSTL
H2, 42
A12
I
SSTL Address Signal 12
Note: 256 Mbit or larger dies
NC
NC
—
Note: 128 Mbit or smaller dies
F9, 17
A13
I
SSTL Address Signal 13
Note: 1 Gbit based dies
NC
NC
—
Note: 512 Mbit or smaller dies
Data Signals ×4 organization
B7, 5
DQ0
I/O
SSTL Data Signal 3:0
D7, 11
DQ1
I/O
SSTL
D3, 56
DQ2
I/O
SSTL
B3, 62
DQ3
I/O
SSTL
Data Strobe ×4 organisation
E3, 51
DQS I/O
SSTL Data Strobe
Note: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write
data.
Data Mask ×4 organization
F3, 47
DM
I
SSTL Data Mask:
Note: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading.
Data Sheet
13
Rev. 1.6, 2004-12